{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T07:27:51Z","timestamp":1768030071673,"version":"3.49.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"ARO","award":["W911NF1910470"],"award-info":[{"award-number":["W911NF1910470"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2022,7,1]]},"DOI":"10.1109\/lca.2022.3215489","type":"journal-article","created":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T23:12:58Z","timestamp":1667517178000},"page":"149-152","source":"Crossref","is-referenced-by-count":3,"title":["A Model for Scalable and Balanced Accelerators for Graph Processing"],"prefix":"10.1109","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1896-1489","authenticated-orcid":false,"given":"Marjan","family":"Fariborz","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahyar","family":"Samani","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Terry","family":"O'Neill","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Lowe-Power","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7420-1871","authenticated-orcid":false,"given":"S.J. Ben","family":"Yoo","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3014-5326","authenticated-orcid":false,"given":"Venkatesh","family":"Akella","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Department of Computer Science, University of California Davis, Davis, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783759"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00053"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.14778\/2809974.2809983"},{"key":"ref9","article-title":"GraphLab: A new framework for parallel machine learning","author":"low","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"ref3","year":"0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3503221.3508403"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00078"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2833179.2833187"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00010"},{"key":"ref2","year":"0"},{"key":"ref1","year":"0"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/9810321\/09928529.pdf?arnumber=9928529","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T16:30:53Z","timestamp":1673454653000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9928529\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,1]]},"references-count":12,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2022.3215489","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,1]]}}}