{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:34:44Z","timestamp":1777127684899,"version":"3.51.4"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"DSSoC DARPA"},{"name":"Stanford AHA Agile Hardware Center and Affiliates Program, Intel's Science and Technology Center"},{"name":"Stanford SystemX Alliance, SRC JUMP 2.0 PRISM Center"},{"name":"NSF CAREER","award":["2238006"],"award-info":[{"award-number":["2238006"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2023,1,1]]},"DOI":"10.1109\/lca.2023.3268126","type":"journal-article","created":{"date-parts":[[2023,4,19]],"date-time":"2023-04-19T17:24:38Z","timestamp":1681925078000},"page":"45-48","source":"Crossref","is-referenced-by-count":9,"title":["Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays"],"prefix":"10.1109","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8232-1603","authenticated-orcid":false,"given":"Jackson","family":"Melchert","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8902-2518","authenticated-orcid":false,"given":"Keyi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9459-5994","authenticated-orcid":false,"given":"Yuchen","family":"Mei","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3245-7542","authenticated-orcid":false,"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2385-619X","authenticated-orcid":false,"given":"Christopher","family":"Torng","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8834-8663","authenticated-orcid":false,"given":"Priyanka","family":"Raina","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830509"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995277"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055187"},{"key":"ref6","article-title":"FPGA routing structures: A novel switch block and depopulated interconnect matrix architectures","author":"Masud","year":"1998"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-6505-7_6"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275134"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00070"},{"key":"ref11","first-page":"7:1","article-title":"A golden age of hardware description languages: Applying programming language techniques to improve design productivity","volume-title":"Proc. 3rd Summit Adv. Program. Lang.","author":"Truong"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-015-7744-1_2"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783755"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00032"},{"key":"ref15","volume-title":"Principles of CMOS VLSI Design: A Systems Perspective","author":"Weste","year":"1993"},{"key":"ref16","article-title":"Architecture and algorithms for field programmable gate arrays with embedded memory","author":"Wilton","year":"1977"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT52863.2021.9609928"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/10208\/10006348\/10105430-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/10006348\/10105430.pdf?arnumber=10105430","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,12]],"date-time":"2024-01-12T02:33:50Z","timestamp":1705026830000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10105430\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1,1]]},"references-count":17,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2023.3268126","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,1,1]]}}}