{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T10:15:24Z","timestamp":1775470524646,"version":"3.50.1"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2023,1]]},"DOI":"10.1109\/lca.2023.3276709","type":"journal-article","created":{"date-parts":[[2023,5,16]],"date-time":"2023-05-16T19:43:49Z","timestamp":1684266229000},"page":"53-56","source":"Crossref","is-referenced-by-count":12,"title":["Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping"],"prefix":"10.1109","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8532-1038","authenticated-orcid":false,"given":"Anurag","family":"Kar","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xueyang","family":"Liu","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3088-5984","authenticated-orcid":false,"given":"Yonghae","family":"Kim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3542-2548","authenticated-orcid":false,"given":"Gururaj","family":"Saileshwar","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6061-7825","authenticated-orcid":false,"given":"Hyesoon","family":"Kim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5738-6942","authenticated-orcid":false,"given":"Tushar","family":"Krishna","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.24"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3479876.3481595"},{"key":"ref12","article-title":"MacSim: A CPU-GPU heterogeneous simulation framework user guide","author":"kim","year":"2012"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00068"},{"key":"ref4","first-page":"2857","article-title":"Don't mesh around: Side-Channel attacks and mitigations on mesh interconnects","author":"dai","year":"2022","journal-title":"Proc 31st USENIX Secur Symp"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00080"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485972"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.25"},{"key":"ref10","article-title":"Mapping the Intel last-level cache","author":"yarom","year":"2015"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SP46214.2022.9833794"},{"key":"ref1","first-page":"645","article-title":"Lord of the ring(s): Side channel attacks on the CPU on-chip ring interconnect are practical","author":"paccagnella","year":"2021","journal-title":"Proc 30th USENIX Secur Symp"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/10006348\/10124988.pdf?arnumber=10124988","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,19]],"date-time":"2023-06-19T17:54:11Z","timestamp":1687197251000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10124988\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2023.3276709","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,1]]}}}