{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T17:03:29Z","timestamp":1785258209526,"version":"3.55.0"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006785","name":"Google","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006785","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Huawei"},{"name":"Intel"},{"DOI":"10.13039\/100004318","name":"Microsoft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004318","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100016682","name":"VMware","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100016682","id-type":"DOI","asserted-by":"publisher"}]},{"name":"SRC"},{"name":"EFCL"},{"name":"InnoHK ACCESS Center"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/lca.2023.3333759","type":"journal-article","created":{"date-parts":[[2023,11,17]],"date-time":"2023-11-17T18:56:48Z","timestamp":1700247408000},"page":"112-116","source":"Crossref","is-referenced-by-count":110,"title":["Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator"],"prefix":"10.1109","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0849-8724","authenticated-orcid":false,"given":"Haocong","family":"Luo","sequence":"first","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9291-3626","authenticated-orcid":false,"given":"Yahya Can","family":"Tu\u011frul","sequence":"additional","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2718-0297","authenticated-orcid":false,"given":"F. Nisa","family":"Bostanc\u0131","sequence":"additional","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5333-5726","authenticated-orcid":false,"given":"Ataberk","family":"Olgun","sequence":"additional","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9333-6077","authenticated-orcid":false,"given":"A. Giray","family":"Ya\u011fl\u0131k\u00e7\u0131","sequence":"additional","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zürich, Zürich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"USIMM: The Utah SImulated memory module","author":"Chatterjee","year":"2012"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2973991"},{"key":"ref5","year":"2020","journal-title":"JESD794C: DDR4 SDRAM Standard"},{"key":"ref6","article-title":"Ramulator2 GitHub repository","volume-title":"SAFARI Research Group","year":"2023"},{"key":"ref7","year":"2020","journal-title":"JESD795: DDR5 SDRAM Standard"},{"key":"ref8","year":"2020","journal-title":"JESD209\u20135A: LPDDR5 SDRAM Standard"},{"key":"ref9","year":"2021","journal-title":"JESD250C: Graphics Double Data Rate 6 (GDDR6) Standard"},{"key":"ref10","year":"2023","journal-title":"JESD238A: High Bandwidth Memory (HBM3) DRAM"},{"key":"ref11","journal-title":"ISO, ISO\/IEC 14882:2020 Programming languages \u2014 C++"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853210"},{"key":"ref13","first-page":"385","article-title":"TWiCe: Preventing row-hammering by exploiting time window counters","volume-title":"Proc. ACM\/IEEE 46th Int. Symp. Comput. Architecture","author":"Lee"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00014"},{"key":"ref15","first-page":"699","article-title":"Hydra: Enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking","volume-title":"Proc. ACM\/IEEE Int. Symp. Comput. Architecture","author":"Kim"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507716"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00059"},{"key":"ref18","article-title":"The gem5 simulator: Version 20.0+","author":"Lowe-Power","year":"2020"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"ref20","year":"2012","journal-title":"JESD79\u20133: DDR3 SDRAM Standard"},{"key":"ref21","year":"2021","journal-title":"JESD235D: High Bandwidth Memory DRAM (HBM1, HBM2)"},{"key":"ref22","article-title":"Micron DDR4 verilog model","volume-title":"Micron Technology","year":"2018"},{"key":"ref23","article-title":"SPEC CPU 2006","volume-title":"Standard Performance Evaluation Corp.","year":"2006"},{"key":"ref24","article-title":"SPEC CPU 2017","volume-title":"Standard Performance Evaluation Corp.","year":"2017"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/10375809\/10321647.pdf?arnumber=10321647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,6]],"date-time":"2024-05-06T17:23:05Z","timestamp":1715016185000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10321647\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":24,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2023.3333759","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}