{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T00:45:37Z","timestamp":1773708337586,"version":"3.50.1"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/lca.2025.3525970","type":"journal-article","created":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T20:03:10Z","timestamp":1736366590000},"page":"21-24","source":"Crossref","is-referenced-by-count":3,"title":["High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2922-0483","authenticated-orcid":false,"given":"Vardhana","family":"M","sequence":"first","affiliation":[{"name":"Qualcomm India Private Ltd., Bangalore, India"}]},{"given":"Rohan","family":"Pinto","sequence":"additional","affiliation":[{"name":"Faculty of Electronics and Communication Engineering, St. Joseph Engineering College, Visvesvaraya Technological University, Belagavi, India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00013"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2897701"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP52443.2021.00045"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2941250"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2767204"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2985727"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2024.3466563"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2961602"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3258411"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3330993"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928682"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3643682"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3296375"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3331225"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3108065"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/10817484\/10833703.pdf?arnumber=10833703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T18:44:12Z","timestamp":1737398652000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10833703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":15,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3525970","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}