{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:11:36Z","timestamp":1774631496059,"version":"3.50.1"},"reference-count":6,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/lca.2025.3530093","type":"journal-article","created":{"date-parts":[[2025,1,14]],"date-time":"2025-01-14T19:44:20Z","timestamp":1736883860000},"page":"37-40","source":"Crossref","is-referenced-by-count":3,"title":["Accelerating Page Migrations in Operating Systems With Intel DSA"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-0599-2028","authenticated-orcid":false,"given":"Jongho","family":"Baik","sequence":"first","affiliation":[{"name":"Ajou University, Gyeonggi-do, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4943-7839","authenticated-orcid":false,"given":"Jonghyeon","family":"Kim","sequence":"additional","affiliation":[{"name":"Ajou University, Gyeonggi-do, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8250-8574","authenticated-orcid":false,"given":"Chang Hyun","family":"Park","sequence":"additional","affiliation":[{"name":"Uppsala University, Uppsala, Sweden"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4503-8294","authenticated-orcid":false,"given":"Jeongseob","family":"Ahn","sequence":"additional","affiliation":[{"name":"Korea University, Seoul, South Korea"}]}],"member":"263","reference":[{"key":"ref4","article-title":"DAMON based 2-tier memory management for CXL memory","author":"Kim","year":"2024"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3620665.3640401"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3502181.3531466"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483550"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304024"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00066"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/10817484\/10841986.pdf?arnumber=10841986","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,20]],"date-time":"2025-02-20T20:09:14Z","timestamp":1740082154000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10841986\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":6,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3530093","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}