{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:44Z","timestamp":1772724824224,"version":"3.50.1"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003130","name":"Fonds Wetenschappelijk Onderzoek","doi-asserted-by":"publisher","award":["G018722N"],"award-info":[{"award-number":["G018722N"]}],"id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003130","name":"Fonds Wetenschappelijk Onderzoek","doi-asserted-by":"publisher","award":["G096225N"],"award-info":[{"award-number":["G096225N"]}],"id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]},{"name":"UGent-BOF-GOA","award":["01G01421"],"award-info":[{"award-number":["01G01421"]}]},{"DOI":"10.13039\/501100005416","name":"Norges Forskningsr\u00e5d","doi-asserted-by":"publisher","award":["286596"],"award-info":[{"award-number":["286596"]}],"id":[{"id":"10.13039\/501100005416","id-type":"DOI","asserted-by":"publisher"}]},{"name":"European Union Horizon 2020 program","award":["101034240"],"award-info":[{"award-number":["101034240"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/lca.2025.3553766","type":"journal-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T17:53:17Z","timestamp":1744221197000},"page":"101-104","source":"Crossref","is-referenced-by-count":2,"title":["Memory-Centric MCM-GPU Architecture"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6310-8954","authenticated-orcid":false,"given":"Hossein","family":"SeyyedAghaei","sequence":"first","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Mahmood","family":"Naderan-Tahan","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, Netherlands"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9147-5228","authenticated-orcid":false,"given":"Magnus","family":"Jahre","sequence":"additional","affiliation":[{"name":"Norwegian University of Science and Technology, Trondheim, Norway"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8792-4473","authenticated-orcid":false,"given":"Lieven","family":"Eeckhout","sequence":"additional","affiliation":[{"name":"Ghent University, Gent, Belgium"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080231"},{"key":"ref2","article-title":"NVIDIA\u2019s next generation CUDA compute architecture: Fermi","year":"2010"},{"key":"ref3","article-title":"NVIDIA Tesla P100","year":"2016"},{"key":"ref4","article-title":"NVIDIA H100 tensor core GPU architecture","year":"2022"},{"key":"ref5","volume-title":"","year":"2021"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00025"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3237927"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00047"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref10","article-title":"Nvidia CUDA SDK code sample","year":"2023"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00021"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2024.3484958"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2024.3458900"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/10817484\/10960372.pdf?arnumber=10960372","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,11]],"date-time":"2025-04-11T17:55:58Z","timestamp":1744394158000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10960372\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":14,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3553766","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}