{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:30:17Z","timestamp":1755221417548,"version":"3.43.0"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1109\/lca.2025.3563728","type":"journal-article","created":{"date-parts":[[2025,4,24]],"date-time":"2025-04-24T14:49:18Z","timestamp":1745506158000},"page":"249-252","source":"Crossref","is-referenced-by-count":0,"title":["Halis: A Hardware-Software Co-Designed Near-Cache Accelerator for Graph Pattern Mining"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-4275-219X","authenticated-orcid":false,"given":"\u015eevval","family":"\u0130zmirli","sequence":"first","affiliation":[{"name":"Computer Engineering Department, TOBB University of Economics and Technology, Ankara, Türkiye"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8291-509X","authenticated-orcid":false,"given":"Julian","family":"Pavon","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5092-3829","authenticated-orcid":false,"given":"Ivan Vargas","family":"Valdivieso","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9117-4750","authenticated-orcid":false,"given":"Bet\u00fcl","family":"Ayde\u011fer","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, TOBB University of Economics and Technology, Ankara, Türkiye"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4131-1468","authenticated-orcid":false,"given":"Kerem","family":"Yal\u00e7\u0131nkaya","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, TOBB University of Economics and Technology, Ankara, Türkiye"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1277-9296","authenticated-orcid":false,"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2701-3787","authenticated-orcid":false,"given":"O\u011fuz","family":"Ergin","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, TOBB University of Economics and Technology, Ankara, Türkiye"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0544-9697","authenticated-orcid":false,"given":"Osman","family":"\u00dcnsal","sequence":"additional","affiliation":[{"name":"Computer Science Department, Barcelona Supercomputing Center, Barcelona, Spain"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00052"},{"article-title":"Graphzero: Breaking symmetry for efficient graph mining","year":"2019","author":"Mawhirter","key":"ref2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527437"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00010"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527388"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SC41405.2020.00104"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00095"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589079"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00081"},{"volume-title":"Intel 64 and IA-32 Architectures Optimization Reference Manual","year":"2023","key":"ref10"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"article-title":"The gap benchmark suite","year":"2017","author":"Beamer","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/11062520\/10974574.pdf?arnumber=10974574","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T18:38:49Z","timestamp":1754678329000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10974574\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7]]},"references-count":13,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3563728","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"type":"print","value":"1556-6056"},{"type":"electronic","value":"1556-6064"},{"type":"electronic","value":"2473-2575"}],"subject":[],"published":{"date-parts":[[2025,7]]}}}