{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:30:17Z","timestamp":1755221417578,"version":"3.43.0"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1109\/lca.2025.3585621","type":"journal-article","created":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T13:27:49Z","timestamp":1751549269000},"page":"237-240","source":"Crossref","is-referenced-by-count":0,"title":["On Internally Tagged Instruction Set Architectures"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3675-3376","authenticated-orcid":false,"given":"Emad Jacob","family":"Maroun","sequence":"first","affiliation":[{"name":"Department of Applied Mathematics and Computer Science, Technical University of Denmark, Kongens Lyngby, Denmark"}]}],"member":"263","reference":[{"article-title":"The impact of ISAs on performance","volume-title":"Proc. Workshop Duplicating, Deconstructing Debunking Co-Located 44th Int. Symp. Comput. Architecture","author":"Akram","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2699682"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413117"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750391"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009130"},{"key":"ref6","first-page":"1","article-title":"The RISC-V Instruction Set Manual Volume I: Unprivileged ISA","volume":"20191213","author":"Waterman","year":"2019","journal-title":"RISC-V Found."},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1478873.1478920"},{"article-title":"Tagged architecture: A quantitative analysis","year":"2005","author":"Hagelberg","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/327070.327153"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3533704"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676495"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898058"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037726"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/11062520\/11066236.pdf?arnumber=11066236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T18:38:49Z","timestamp":1754678329000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11066236\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7]]},"references-count":13,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3585621","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"type":"print","value":"1556-6056"},{"type":"electronic","value":"1556-6064"},{"type":"electronic","value":"2473-2575"}],"subject":[],"published":{"date-parts":[[2025,7]]}}}