{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T05:40:02Z","timestamp":1756791602404,"version":"3.44.0"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T00:00:00Z","timestamp":1751328000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"NSF","award":["PPoSS-2217071","FA-8075-18-D-0004"],"award-info":[{"award-number":["PPoSS-2217071","FA-8075-18-D-0004"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2025,7]]},"DOI":"10.1109\/lca.2025.3600588","type":"journal-article","created":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T18:14:38Z","timestamp":1755627278000},"page":"277-280","source":"Crossref","is-referenced-by-count":0,"title":["PIMsynth: A Unified Compiler Framework for Bit-Serial Processing-in-Memory Architectures"],"prefix":"10.1109","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-1756-1784","authenticated-orcid":false,"given":"Deyuan","family":"Guo","sequence":"first","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5549-2901","authenticated-orcid":false,"given":"Mohammadhosein","family":"Gholamrezaei","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Hofmann","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ashish","family":"Venkat","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0778-0308","authenticated-orcid":false,"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8091-9302","authenticated-orcid":false,"given":"Kevin","family":"Skadron","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"273","article-title":"Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology","volume-title":"Proc. Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Seshadri"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00033"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00024"},{"key":"ref6","first-page":"288","article-title":"DRISA: A DRAM-based reconfigurable in-situ accelerator","volume-title":"Proc. Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Li"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.3211117"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539721"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC63097.2024.00030"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10071070"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-45727-3_11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"article-title":"Yosys open synthesis suite","year":"2016","author":"Wolf","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546754"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00061"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00019"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/10208\/11062520\/11130365-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/11062520\/11130365.pdf?arnumber=11130365","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T05:01:48Z","timestamp":1756789308000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130365\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7]]},"references-count":17,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2025.3600588","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"type":"print","value":"1556-6056"},{"type":"electronic","value":"1556-6064"},{"type":"electronic","value":"2473-2575"}],"subject":[],"published":{"date-parts":[[2025,7]]}}}