{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T09:28:54Z","timestamp":1773998934603,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1109\/lca.2026.3668463","type":"journal-article","created":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T20:48:30Z","timestamp":1772225310000},"page":"93-96","source":"Crossref","is-referenced-by-count":0,"title":["CMM-H PMEM: Performance Characterization of CXL Large Capacity Persistent Memory"],"prefix":"10.1109","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-5420-1361","authenticated-orcid":false,"given":"Gongjin","family":"Sun","sequence":"first","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-7097-2488","authenticated-orcid":false,"given":"Mehdi","family":"Nik","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0403-8704","authenticated-orcid":false,"given":"Senthil","family":"Murugesapandian","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-3415-709X","authenticated-orcid":false,"given":"Dongyang","family":"Li","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kwan","family":"Huen","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2731-4807","authenticated-orcid":false,"given":"Xuebin","family":"Yao","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-0601-0410","authenticated-orcid":false,"given":"Caroline","family":"Kahn","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9621-4656","authenticated-orcid":false,"given":"Amir","family":"Beygi","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0580-5716","authenticated-orcid":false,"given":"Vitorio","family":"Cargnini","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-0909-8488","authenticated-orcid":false,"given":"Ramdas","family":"Kachare","sequence":"additional","affiliation":[{"name":"Memory Solutions Lab, Samsung Semiconductor, Inc., San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3669900"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3736548.3737828"},{"key":"ref3","article-title":"Basic performance measurements of the Intel Optane DC persistent memory module","author":"Izraelevitz","year":"2019"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3605946"},{"key":"ref5","first-page":"323","article-title":"NOVA: A log-structured file system for hybrid volatile\/non-volatile main memories","volume-title":"Proc. 14th USENIX Conf. File Storage Technol.","volume":"16","author":"Xu","year":"2016"},{"key":"ref6","first-page":"1","article-title":"The fundamental limit of flash random write performance: Understanding, analysis and performance modelling","volume":"3771","author":"Hu","year":"2010","journal-title":"IBM Res. Rep. RZ"},{"key":"ref8","article-title":"Samsung PM9A3 NVMe SSD","year":"2025"},{"key":"ref9","article-title":"Intel memory latency checker (v3.11a)","year":"2025"},{"issue":"45\u201374","key":"ref10","article-title":"Introducing the graph 500","volume":"19","author":"Murphy","year":"2010","journal-title":"Cray Users Group"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1773912.1773922"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3465402"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3033273"},{"key":"ref14","first-page":"753","article-title":"$\\lbrace${SILK $\\rbrace$}: Preventing latency spikes in $\\lbrace${Log-Structured$\\rbrace$} merge $\\lbrace${Key-Value$\\rbrace$} stores","volume-title":"Proc. USENIX Annu. Tech. Conf.","author":"Balmau","year":"2019"},{"key":"ref15","first-page":"373","article-title":"$\\lbrace${RIPQ$\\rbrace$}: Advanced photo caching on flash for facebook","volume-title":"Proc. 13th USENIX Conf. File Storage Technol.","author":"Tang","year":"2015"},{"key":"ref16","first-page":"65","article-title":"Flashield: A hybrid key-value cache that controls flash write amplification","volume-title":"Proc. 16th USENIX Symp. Netw. Syst. Des. Implementation","author":"Eisenman","year":"2019"},{"key":"ref17","article-title":"Samsung CMM-D","year":"2025"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3358861"},{"key":"ref19","article-title":"Optimizing system memory bandwidth with micron CXL memory expansion modules on Intel Xeon 6 processors","author":"Sehgal","year":"2024"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10208\/11321093\/11415655.pdf?arnumber=11415655","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T05:51:33Z","timestamp":1773985893000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11415655\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":18,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2026.3668463","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,1]]}}}