{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,12]],"date-time":"2024-11-12T05:17:21Z","timestamp":1731388641673,"version":"3.28.0"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/les.2010.2049983","type":"journal-article","created":{"date-parts":[[2010,5,21]],"date-time":"2010-05-21T20:58:34Z","timestamp":1274475514000},"page":"53-57","source":"Crossref","is-referenced-by-count":0,"title":["Towards Fully Automatic Synthesis of Embedded Software"],"prefix":"10.1109","volume":"2","author":[{"given":"Ulrich","family":"Kuhne","sequence":"first","affiliation":[{"name":"Dept. of Comput. Sci., Univ. of Bremen, Bremen, Germany"}]},{"given":"Daniel","family":"Gro\u00dfe","sequence":"additional","affiliation":[{"name":"Dept. of Comput. Sci., Univ. of Bremen, Bremen, Germany"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Dept. of Comput. Sci., Univ. of Bremen, Bremen, Germany"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512566"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379071"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358108"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSIM.2009.5195312"},{"key":"ref14","first-page":"240","article-title":"a performance-driven qbf-based iterative logic array representation with applications to verification, debug and test","author":"mangassarian","year":"2007","journal-title":"Proc Int Conf Comput Aided Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/2.161279"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156196"},{"journal-title":"Computational Complexity","year":"1994","author":"papadimitriou","key":"ref17"},{"journal-title":"Accellera Property Specification Language Reference Manual Version 1 1","year":"2005","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISoLA.2006.62"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1995.1025"},{"key":"ref3","first-page":"193","article-title":"symbolic model checking without bdds","author":"biere","year":"1999","journal-title":"Proc Int Conf Tools Algorithms Construction Analy Syst"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-005-0004-8"},{"key":"ref5","first-page":"368","article-title":"behavioral consistency of c and verilog programs using bounded model checking","author":"clarke","year":"2003","journal-title":"Proc Design Autom Conf"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"502","DOI":"10.1007\/978-3-540-24605-3_37","article-title":"An extensible SAT solver","author":"en","year":"2004","journal-title":"Proc Int Conf Theory Appl Satisfiability Testing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923410"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.5381\/jot.2004.3.6.a2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-4538-2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1109118.1109123"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1168918.1168907"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2009.21"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1707801.1706337"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4563995\/5577467\/05462901.pdf?arnumber=5462901","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,11]],"date-time":"2024-11-11T18:41:27Z","timestamp":1731350487000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/5462901\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":22,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/les.2010.2049983","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"type":"print","value":"1943-0663"},{"type":"electronic","value":"1943-0671"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}