{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T08:02:23Z","timestamp":1706774543282},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2011,9,1]],"date-time":"2011-09-01T00:00:00Z","timestamp":1314835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/les.2011.2167213","type":"journal-article","created":{"date-parts":[[2011,9,15]],"date-time":"2011-09-15T05:19:43Z","timestamp":1316063983000},"page":"89-92","source":"Crossref","is-referenced-by-count":11,"title":["A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems"],"prefix":"10.1109","volume":"3","author":[{"family":"Qian Zhao","sequence":"first","affiliation":[]},{"given":"Y.","family":"Ichinomiya","sequence":"additional","affiliation":[]},{"given":"M.","family":"Amagasaki","sequence":"additional","affiliation":[]},{"given":"M.","family":"Iida","sequence":"additional","affiliation":[]},{"given":"T.","family":"Sueyoshi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296426"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref14","first-page":"448","article-title":"Soft-error tolerability analysis for triplicated circuit on an FPGA","author":"ichinomiya","year":"2010","journal-title":"Proc SASIMI2010"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272319"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033796"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611834"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.25"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2008.4538760"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2007.5205603"},{"key":"ref2","year":"2007","journal-title":"Single-Event Effects in FPGAs"},{"key":"ref1","year":"2010","journal-title":"Device Reliability Report"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681775"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4563995\/6059669\/06009172.pdf?arnumber=6009172","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:16Z","timestamp":1633909576000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6009172\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":14,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/les.2011.2167213","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,9]]}}}