{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T22:46:08Z","timestamp":1747867568366},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/les.2013.2280582","type":"journal-article","created":{"date-parts":[[2013,9,5]],"date-time":"2013-09-05T18:03:04Z","timestamp":1378404184000},"page":"65-68","source":"Crossref","is-referenced-by-count":2,"title":["Fast Filter-Based Boolean Matchers"],"prefix":"10.1109","volume":"5","author":[{"given":"Chaofan","family":"Yu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingli","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"He","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681549"},{"key":"ref11","year":"0","journal-title":"Bloom filter"},{"key":"ref12","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref13","year":"0","journal-title":"IWLS 2005Benchmarks"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E93.A.1775"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147034"},{"key":"ref4","first-page":"350","article-title":"Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping","author":"hu","year":"2007","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243959"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193838"},{"key":"ref5","first-page":"597","article-title":"Lazy Man?s Synthesis","author":"yang","year":"2012","journal-title":"Proc Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723145"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/264995.264996"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065693"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.945303"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654275"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4563995\/6663221\/06589119.pdf?arnumber=6589119","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:11Z","timestamp":1642004651000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6589119\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":15,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/les.2013.2280582","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,12]]}}}