{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:14:26Z","timestamp":1781885666134,"version":"3.54.5"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2017,12,1]],"date-time":"2017-12-01T00:00:00Z","timestamp":1512086400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"European Unions Horizon 2020 Research and Innovation Program for the Oprecomp Project","award":["732631"],"award-info":[{"award-number":["732631"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2017,12]]},"DOI":"10.1109\/les.2017.2707978","type":"journal-article","created":{"date-parts":[[2017,5,24]],"date-time":"2017-05-24T18:20:22Z","timestamp":1495650022000},"page":"125-128","source":"Crossref","is-referenced-by-count":4,"title":["A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4623-1731","authenticated-orcid":false,"given":"Maryam","family":"Payami","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Erfan","family":"Azarkhish","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Igor","family":"Loi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2890498"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477325"},{"key":"ref10","article-title":"Instruction prefetching techniques for ultra low-power multicore architectures","author":"payami","year":"2016"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxt129"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2742854.2747288"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2907071"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2014.2326895"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2016.2519521"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133384"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01743-8","author":"falsafi","year":"2014","journal-title":"A Primer on Hardware Prefetching"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4563995\/8114509\/07933223.pdf?arnumber=7933223","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,23]],"date-time":"2023-08-23T18:36:37Z","timestamp":1692815797000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7933223\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12]]},"references-count":11,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/les.2017.2707978","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,12]]}}}