{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,3]],"date-time":"2026-05-03T05:44:04Z","timestamp":1777787044379,"version":"3.51.4"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1109\/les.2021.3122395","type":"journal-article","created":{"date-parts":[[2021,10,25]],"date-time":"2021-10-25T19:48:54Z","timestamp":1635191334000},"page":"99-102","source":"Crossref","is-referenced-by-count":3,"title":["Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs"],"prefix":"10.1109","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0003-3318","authenticated-orcid":false,"given":"Ignacio M.","family":"Delgado-Lozano","sequence":"first","affiliation":[{"name":"Network and Information Security Group, Tampere University, Tampere, Finland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8905-5715","authenticated-orcid":false,"given":"Erica","family":"Tena-Sanchez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0279-9472","authenticated-orcid":false,"given":"Juan","family":"Nunez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio J.","family":"Acosta","sequence":"additional","affiliation":[{"name":"Instituto de Microelectrónica de Sevilla (IMSE-CNM) (joint research centre by Universidad de Sevilla and CSIC), Seville, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2014.6881441"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2015.2390591"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.3390\/electronics6030067"},{"issue":"2","key":"ref4","first-page":"271","article-title":"Security analysis of tunnel field-effect transistor for low power hardware","volume":"8","author":"Taheri","year":"2017","journal-title":"Int. J. Comput. Sci. Inf. Tech. (IJCSIT)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-125"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-38162-6"},{"key":"ref7","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","volume-title":"Proc. Eur. Solid-State Circuits Conf. (ESSCIRC)","author":"Tiri"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2315878"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2015.2418033"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/nature10679"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.149"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293153"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2616891"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2559159"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3381857"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2109002"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2017.2737598"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/1-4020-8147-2_10"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2014.72"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-44371-2_4"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4563995\/9782462\/09585297.pdf?arnumber=9585297","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T22:28:58Z","timestamp":1705012138000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9585297\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6]]},"references-count":20,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/les.2021.3122395","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6]]}}}