{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T20:55:41Z","timestamp":1774126541150,"version":"3.50.1"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2024,12]]},"DOI":"10.1109\/les.2024.3364698","type":"journal-article","created":{"date-parts":[[2024,2,12]],"date-time":"2024-02-12T19:16:01Z","timestamp":1707765361000},"page":"417-420","source":"Crossref","is-referenced-by-count":16,"title":["High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications"],"prefix":"10.1109","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3295-2028","authenticated-orcid":false,"given":"Mitul Sudhirkumar","family":"Nagar","sequence":"first","affiliation":[{"name":"Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India"}]},{"given":"Aditya","family":"Mathuriya","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India"}]},{"given":"Sohan H.","family":"Patel","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4955-232X","authenticated-orcid":false,"given":"Pinalkumar J.","family":"Engineer","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465781"},{"key":"ref2","volume-title":"Integer Arithmetic IP Cores User Guide","year":"2017"},{"key":"ref3","volume-title":"LogiCORE IP multiplier v12.0","year":"2015"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2015.17"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.48"},{"key":"ref6","article-title":"Fast multiplication: Algorithms and implementation","author":"Bewick","year":"1994"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.2995053"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00011"},{"key":"ref9","volume-title":"Versal ACAP DSP Engine Architecture Manual (AM004)","year":"2020"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00027"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2018.8464695"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272301"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.3390\/computers5040020"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref15","first-page":"349","article-title":"Some schemes for parallel multipliers","volume":"34","author":"Dadda","year":"1965","journal-title":"Alta Frequenza"},{"key":"ref16","first-page":"171","article-title":"An efficient high speed compression trees on Xilinx FPGAs","volume-title":"Proc. Methods Descr. Lang. Model. Verif. Circuits Syst. (MBMV)","author":"Kumm"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.51"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926993"},{"key":"ref20","volume-title":"LeNet-5","author":"Ahmed","year":"2023"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4563995\/10779572\/10433009.pdf?arnumber=10433009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T01:30:39Z","timestamp":1733880639000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10433009\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12]]},"references-count":20,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/les.2024.3364698","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,12]]}}}