{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T15:05:46Z","timestamp":1777129546621,"version":"3.51.4"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2025,2]]},"DOI":"10.1109\/les.2024.3435477","type":"journal-article","created":{"date-parts":[[2024,7,29]],"date-time":"2024-07-29T18:02:04Z","timestamp":1722276124000},"page":"62-65","source":"Crossref","is-referenced-by-count":3,"title":["Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques"],"prefix":"10.1109","volume":"17","author":[{"given":"Ricardo","family":"Paez Villa","sequence":"first","affiliation":[{"name":"Electrical Engineering Department, Centro de Investigaci&#x00C3;n y de Estudios Avanzados, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, M&#x00E9;xico"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0978-2224","authenticated-orcid":false,"given":"Jorge","family":"Rivera","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Centro de Investigaci&#x00C3;n y de Estudios Avanzados, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, M&#x00E9;xico"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8567-4981","authenticated-orcid":false,"given":"Juan","family":"Jos\u00e9 Raygoza","sequence":"additional","affiliation":[{"name":"Department of Electro-Photonics, Universidad de Guadalajara Centro Universitario de Ciencias Exactas e Ingenieria, Guadalajara, Mexico"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0596-9035","authenticated-orcid":false,"given":"Edwin","family":"Becerra","sequence":"additional","affiliation":[{"name":"Department of Electro-Photonics, Universidad de Guadalajara Centro Universitario de Ciencias Exactas e Ingenieria, Guadalajara, Mexico"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6646-1529","authenticated-orcid":false,"given":"Susana","family":"Ortega","sequence":"additional","affiliation":[{"name":"Electrical Engineering Department, Centro de Investigaci&#x00C3;n y de Estudios Avanzados, CINVESTAV del IPN, Unidad Guadalajara, Zapopan, M&#x00E9;xico"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/ICEMS50442.2020.9290816"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3187515"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/PECON.2016.7951616"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.04.004"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.11591\/ijpeds.v11.i3.pp1153-1164"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.40"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2878599"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.30941\/CESTEMS.2022.00020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.3390\/computation7030041"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2018.8406022"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/1314\/1\/012008"},{"key":"ref12","volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","author":"Parhi","year":"1999"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/iccd.1996.563604"},{"key":"ref14","first-page":"9","article-title":"Cost\/performance trade-off of n-select square root implementations","volume-title":"Proc. 5th ACAC","author":"Chu"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4563995\/10887051\/10614228.pdf?arnumber=10614228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T18:51:05Z","timestamp":1739991065000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10614228\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2]]},"references-count":14,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/les.2024.3435477","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2]]}}}