{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,19]],"date-time":"2025-12-19T10:09:47Z","timestamp":1766138987227,"version":"3.37.3"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,1]],"date-time":"2024-12-01T00:00:00Z","timestamp":1733011200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2024,12]]},"DOI":"10.1109\/les.2024.3447695","type":"journal-article","created":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T19:08:48Z","timestamp":1733425728000},"page":"373-376","source":"Crossref","is-referenced-by-count":1,"title":["Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures"],"prefix":"10.1109","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-9184-5996","authenticated-orcid":false,"given":"Kevin J.","family":"Phillipson","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-3863-0727","authenticated-orcid":false,"given":"Michael G.","family":"Rywalt","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2688-281X","authenticated-orcid":false,"given":"Baibhab","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4110-1898","authenticated-orcid":false,"given":"Eric M.","family":"Schwartz","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7159-7439","authenticated-orcid":false,"given":"Greg","family":"Stitt","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2019.2949620"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1989.63352"},{"volume-title":"Modern Processor Design: Fundamentals of Superscalar Processors","year":"2005","author":"Shen","key":"ref3"},{"volume-title":"The VIA Isaiah Architecture","year":"2008","author":"Henry","key":"ref4"},{"volume-title":"Computer Organization and Design RISC-V Edition: The Hardware Software Interface","year":"2017","author":"Patterson","key":"ref5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1201\/9781003574217"},{"volume-title":"Turbo9\u2014A compact & efficient pipelined 6809 microprocessor IP","year":"2024","author":"Phillipson","key":"ref7"},{"article-title":"A compact and efficient microprocessor IP for SoC sub-blocks and mixed-signal ASICs","year":"2022","author":"Phillipson","key":"ref8"},{"issue":"3","key":"ref9","doi-asserted-by":"crossref","first-page":"1978","DOI":"10.3390\/electronics13101978","article-title":"A novel approach to managing system-on-chip sub-blocks using a 16-bit real-time operating system","volume":"13","author":"Pitre","year":"2024","journal-title":"Electronics"},{"volume-title":"A Microprocessor for the Revolution: The 6809","year":"1979","author":"Ritter","key":"ref10"},{"volume-title":"Cycle accurate MC6809 core","year":"2023","author":"Miller","key":"ref11"},{"volume-title":"Overview: AVR core: OpenCores","year":"2017","author":"Lepetenok","key":"ref12"},{"volume-title":"PicoRV32 - a size-Optimized RISC-V CPU","year":"2023","author":"Wolf","key":"ref13"},{"article-title":"Advanced compiling techniques to reduce RAM usage of static operating systems","year":"2004","author":"Barthelmann","key":"ref14"},{"key":"ref15","first-page":"1","article-title":"Building OpenLANE: A 130nm OpenROAD-based tapeout- proven flow: Invited paper","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Shalan"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4563995\/10779572\/10779513.pdf?arnumber=10779513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T01:30:44Z","timestamp":1733880644000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10779513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12]]},"references-count":15,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/les.2024.3447695","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"type":"print","value":"1943-0663"},{"type":"electronic","value":"1943-0671"}],"subject":[],"published":{"date-parts":[[2024,12]]}}}