{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,13]],"date-time":"2026-02-13T21:34:05Z","timestamp":1771018445794,"version":"3.50.1"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100014440","name":"Ministerio de Ciencia, Innovaci?n y Universidades","doi-asserted-by":"publisher","award":["IJC-2020-045931-I"],"award-info":[{"award-number":["IJC-2020-045931-I"]}],"id":[{"id":"10.13039\/100014440","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100014440","name":"Ministerio de Ciencia, Innovaci?n y Universidades","doi-asserted-by":"publisher","award":["PLEC2023-010240"],"award-info":[{"award-number":["PLEC2023-010240"]}],"id":[{"id":"10.13039\/100014440","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministerio para la Transformaci?n Digital y de la Funci?n P?blica","award":["C005\/24-ED CV1"],"award-info":[{"award-number":["C005\/24-ED CV1"]}]},{"DOI":"10.13039\/100010661","name":"Horizon 2020 Framework Programme","doi-asserted-by":"publisher","award":["GA 101069595"],"award-info":[{"award-number":["GA 101069595"]}],"id":[{"id":"10.13039\/100010661","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Embedded Syst. Lett."],"published-print":{"date-parts":[[2026,2]]},"DOI":"10.1109\/les.2025.3560428","type":"journal-article","created":{"date-parts":[[2025,4,14]],"date-time":"2025-04-14T13:39:31Z","timestamp":1744637971000},"page":"64-68","source":"Crossref","is-referenced-by-count":0,"title":["Assessing the Use of NVIDIA Multi-Instance GPU in the Automotive Domain"],"prefix":"10.1109","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1469-2514","authenticated-orcid":false,"given":"Javier","family":"Barrera","sequence":"first","affiliation":[{"name":"High-Performance Embedded System (HPES) Laboratory, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9751-1058","authenticated-orcid":false,"given":"Leonidas","family":"Kosmidis","sequence":"additional","affiliation":[{"name":"High-Performance Embedded System (HPES) Laboratory, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7951-4028","authenticated-orcid":false,"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"High-Performance Embedded System (HPES) Laboratory, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3344-376X","authenticated-orcid":false,"given":"Francisco J.","family":"Cazorla","sequence":"additional","affiliation":[{"name":"High-Performance Embedded System (HPES) Laboratory, Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"NVIDIA Jetson Orin.","year":"2024"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2380356.2380389"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS58335.2023.00012"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2019.00011"},{"key":"ref5","article-title":"Missile: Fine-grained, hardware-level GPU resource isolation for multi-tenant DNN inference","author":"Zhang","year":"2024","journal-title":"arXiv:2407.13996v2"},{"key":"ref6","volume-title":"Multi-Process Service.","year":"2024"},{"key":"ref7","volume-title":"NVIDIA Multi-Instance GPU","year":"2024"},{"key":"ref8","volume-title":"NVIDIA A100 tensor core GPU architecture","year":"2024"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS59052.2023.00031"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643473"},{"key":"ref12","first-page":"23","article-title":"Analysis of memory-contention in heterogeneous COTS MPSoCs","volume-title":"Proc. ECRTS","author":"Hassan"}],"container-title":["IEEE Embedded Systems Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4563995\/11395183\/10964265.pdf?arnumber=10964265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,13]],"date-time":"2026-02-13T20:50:19Z","timestamp":1771015819000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10964265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/les.2025.3560428","relation":{},"ISSN":["1943-0663","1943-0671"],"issn-type":[{"value":"1943-0663","type":"print"},{"value":"1943-0671","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,2]]}}}