{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T10:28:48Z","timestamp":1777631328042,"version":"3.51.4"},"reference-count":42,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11]]},"DOI":"10.1109\/llvmhpchipar51896.2020.00013","type":"proceedings-article","created":{"date-parts":[[2021,1,13]],"date-time":"2021-01-13T00:04:29Z","timestamp":1610496269000},"page":"74-84","source":"Crossref","is-referenced-by-count":3,"title":["A Case Study and Characterization of a Many-socket, Multi-tier NUMA HPC Platform"],"prefix":"10.1109","author":[{"given":"Connor","family":"Imes","sequence":"first","affiliation":[{"name":"USC Information Sciences Institute,Arlington,VA,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven","family":"Hofmeyr","sequence":"additional","affiliation":[{"name":"Lawrence Berkeley National Laboratory,Berkeley,CA,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong In D.","family":"Kang","sequence":"additional","affiliation":[{"name":"USC Information Sciences Institute,Arlington,VA,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John Paul","family":"Walters","sequence":"additional","affiliation":[{"name":"USC Information Sciences Institute,Arlington,VA,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"XSBench - the development and verification of a performance abstraction for monte carlo reactor analysis","author":"tramm","year":"2014","journal-title":"PHYSOR"},{"key":"ref38","author":"trader","year":"2020","journal-title":"Neocortex will be first-of-its-kind 800 000-core ai supercomputer"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3330345.3330376"},{"key":"ref32","year":"2020","journal-title":"Processor counter monitor (PCM)"},{"key":"ref31","article-title":"Memory bandwidth and machine balance in current high performance computers","author":"mccalpin","year":"1995","journal-title":"IEEE TCCA Newsletter"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-20119-1_28"},{"key":"ref37","author":"trader","year":"2020","journal-title":"Intel debuts cooper lake xeons for 4- and 8-socket platforms"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3205289.3205310"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542340"},{"key":"ref34","author":"release","year":"2017","journal-title":"Hpe partners with stephen hawking's cosmos research group and the cambridge faculty of mathematics"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337893"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2018.00055"},{"key":"ref11","year":"2020","journal-title":"Cori for jgi"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.4297"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967946"},{"key":"ref14","author":"enterprise","year":"2020","journal-title":"HPE superdome flex servers"},{"key":"ref15","author":"facility","year":"2020","journal-title":"Aurora - argonne leadership computing facility"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2771937.2771948"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807664"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2018.00013"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3295500.3356150"},{"key":"ref28","author":"laboratory","year":"2019","journal-title":"HPC IO Benchmark Repository"},{"key":"ref4","article-title":"Modeling and optimizing numa effects and prefetching with machine learning","author":"barrera","year":"2020","journal-title":"ICS"},{"key":"ref27","article-title":"Exascale computing study: Technology challenges in achieving ex-ascale systems","volume":"15","author":"kogge","year":"2008","journal-title":"DARPA IPTO Techinal Representative"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3399666.3399910"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-50743-5_17"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/btv033"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2019.8916319"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926279"},{"key":"ref7","author":"berry","year":"0","journal-title":"Machine learning and understanding for intelligent extreme scale scientific computing and discovery"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125925"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840883"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926289"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0168-9274(01)00115-5"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICAC.2019.00015"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-020-67416-5"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926965"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807638"},{"key":"ref41","author":"viswanathan","year":"2020","journal-title":"Intel memory latency checker v3 9"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3225058.3225088"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CPSNA.2015.23"},{"key":"ref25","article-title":"Scalable parallel file write from a large numa system","author":"kang","year":"2020","journal-title":"HPEC"}],"event":{"name":"2020 IEEE\/ACM 6th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) and Workshop on Hierarchical Parallelism for Exascale Computing (HiPar)","location":"GA, USA","start":{"date-parts":[[2020,11,12]]},"end":{"date-parts":[[2020,11,12]]}},"container-title":["2020 IEEE\/ACM 6th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) and Workshop on Hierarchical Parallelism for Exascale Computing (HiPar)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9306857\/9306935\/09306956.pdf?arnumber=9306956","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T17:56:45Z","timestamp":1656439005000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9306956\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/llvmhpchipar51896.2020.00013","relation":{},"subject":[],"published":{"date-parts":[[2020,11]]}}}