{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T09:54:01Z","timestamp":1769075641376,"version":"3.49.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB2803401"],"award-info":[{"award-number":["2022YFB2803401"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Solid-State Circuits Lett."],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/lssc.2025.3589568","type":"journal-article","created":{"date-parts":[[2025,7,16]],"date-time":"2025-07-16T17:40:41Z","timestamp":1752687641000},"page":"237-240","source":"Crossref","is-referenced-by-count":1,"title":["A Dual-Path SPD\/PFD PLL With PVT-Insensitive Loop Bandwidth"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-4411-083X","authenticated-orcid":false,"given":"Yan","family":"Chen","sequence":"first","affiliation":[{"name":"College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-8723-199X","authenticated-orcid":false,"given":"Gaofeng","family":"Jin","sequence":"additional","affiliation":[{"name":"College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8493-6882","authenticated-orcid":false,"given":"Haojie","family":"Xu","sequence":"additional","affiliation":[{"name":"College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Cui","sequence":"additional","affiliation":[{"name":"College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Zeng","sequence":"additional","affiliation":[{"name":"Joywell Semiconductor, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-8627-3247","authenticated-orcid":false,"given":"Xiang","family":"Gao","sequence":"additional","affiliation":[{"name":"College of Integrated Circuits, Zhejiang University, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2791486"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2359719"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LMWT.2023.3307733"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417963"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2899726"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239114"},{"key":"ref8","first-page":"6403","article-title":"A 5.5-7.3 GHz analog fractional-N sampling PLL in 28-nm CMOS with 75 fs rms Jitter and -249.7 dB FoM","volume-title":"Proc. RFIC","author":"Wu"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC60959.2024.10529091"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC57935.2023.10121220"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731578"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365775"}],"container-title":["IEEE Solid-State Circuits Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8011414\/10804564\/11082263.pdf?arnumber=11082263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:33:24Z","timestamp":1756319604000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11082263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/lssc.2025.3589568","relation":{},"ISSN":["2573-9603"],"issn-type":[{"value":"2573-9603","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]}}}