{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,16]],"date-time":"2025-10-16T07:05:51Z","timestamp":1760598351835,"version":"3.43.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"SRC through the Center on COGNISENSE and DARPA through the program on OPTIMA"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Solid-State Circuits Lett."],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/lssc.2025.3590757","type":"journal-article","created":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:08:16Z","timestamp":1753207696000},"page":"213-216","source":"Crossref","is-referenced-by-count":1,"title":["MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-5081-1730","authenticated-orcid":false,"given":"Wei-Chun","family":"Wang","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4187-4428","authenticated-orcid":false,"given":"Shida","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"given":"Laith","family":"Shamieh","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"given":"Narasimha Vasishta","family":"Kidambi","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-6060-5312","authenticated-orcid":false,"given":"Isha","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8894-3390","authenticated-orcid":false,"given":"Saibal","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RWS56914.2024.10438565"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE58400.2024.10546823"},{"key":"ref3","article-title":"Memory is all you need: An overview of compute-in-memory architectures for accelerating large language model inference","author":"Wolters","year":"2024","journal-title":"arXiv:2406.08413"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC60959.2024.10529048"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268706"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-022-04992-8"},{"key":"ref7","article-title":"A white paper on neural network quantization","author":"Nagel","year":"2021","journal-title":"arXiv:2106.08295"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3232601"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365932"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3119018"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731762"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067285"}],"container-title":["IEEE Solid-State Circuits Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8011414\/10804564\/11087240.pdf?arnumber=11087240","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,13]],"date-time":"2025-08-13T17:36:31Z","timestamp":1755106591000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11087240\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/lssc.2025.3590757","relation":{},"ISSN":["2573-9603"],"issn-type":[{"type":"electronic","value":"2573-9603"}],"subject":[],"published":{"date-parts":[[2025]]}}}