{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T05:59:15Z","timestamp":1781243955249,"version":"3.54.1"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Defense Advanced Research Projects Agency (DARPA) Optimum Processing Technology Inside Memory Arrays (OPTIMA) program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Solid-State Circuits Lett."],"published-print":{"date-parts":[[2026]]},"DOI":"10.1109\/lssc.2026.3697990","type":"journal-article","created":{"date-parts":[[2026,5,28]],"date-time":"2026-05-28T22:55:45Z","timestamp":1780008945000},"page":"174-177","source":"Crossref","is-referenced-by-count":0,"title":["A 194.6-TOPS\/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-7304-3595","authenticated-orcid":false,"given":"Saideep","family":"Cherukuri","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"N. V.","family":"Kidambi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-5081-1730","authenticated-orcid":false,"given":"W. C.","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-6060-5312","authenticated-orcid":false,"given":"I.","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4187-4428","authenticated-orcid":false,"given":"S.","family":"Zhang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"L.","family":"Shamieh","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J. B.","family":"Steinberg","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8894-3390","authenticated-orcid":false,"given":"S.","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268706"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2025.3590757"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2025.3539736"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2025.3582752"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2984161"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3119018"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3232601"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3517333"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2024.3382479"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-023-40770-4"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3334566"}],"container-title":["IEEE Solid-State Circuits Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/8011414\/11288938\/11538154.pdf?arnumber=11538154","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T05:39:08Z","timestamp":1781242748000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11538154\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/lssc.2026.3697990","relation":{},"ISSN":["2573-9603"],"issn-type":[{"value":"2573-9603","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]}}}