{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,10]],"date-time":"2025-09-10T21:51:46Z","timestamp":1757541106485},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[1979,6,1]],"date-time":"1979-06-01T00:00:00Z","timestamp":297043200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computer"],"published-print":{"date-parts":[[1979,6]]},"DOI":"10.1109\/mc.1979.1658780","type":"journal-article","created":{"date-parts":[[2007,9,4]],"date-time":"2007-09-04T20:35:32Z","timestamp":1188938132000},"page":"57-65","source":"Crossref","is-referenced-by-count":105,"title":["Interconnection Networks for SIMD Machines"],"prefix":"10.1109","volume":"12","author":[{"family":"Siegel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/800090.802913"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/800123.803967"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.2307\/2309564"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1137\/1003059"},{"key":"ref31","first-page":"209","article-title":"implementation of data manipulating functions on the staran associative processor","author":"bauer","year":"1974","journal-title":"Proc 1974 Sagamore Comput Conf Parallel Processing"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.5009297"},{"key":"ref37","first-page":"206","article-title":"recirculating, pipelined, and multistage simd interconnection networks","author":"smith","year":"1978","journal-title":"Proc 1978 Int'l Conf Parallel Processing"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223927"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.5009205"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223205"},{"key":"ref10","first-page":"287","article-title":"a special computer architecture for image processing","author":"keng","year":"1978","journal-title":"1978 IEEE Comp Soc Conf Pattern Recognition and Image Processing"},{"key":"ref40","first-page":"197","article-title":"routing techniques for a class of multistage interconnection networks","author":"wu","year":"1978","journal-title":"Proc 1978 Int'l Conf Parallel Processing"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.5009291"},{"key":"ref12","first-page":"125","article-title":"a reconfigurable varistructure array processor","author":"lipovski","year":"1977","journal-title":"1977 Int'l Conf Parallel Processing"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1977.231176"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1978.217941"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675732"},{"key":"ref16","first-page":"9","article-title":"control of a partitionable multimicroprocessor system","author":"siegel","year":"1978","journal-title":"Proc 1978 Int'l Conf Parallel Processing"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1979.1658777"},{"key":"ref18","first-page":"387","article-title":"a survey of interconnection methods for reconfigurable parallel processing systems","volume":"48","author":"siegel","year":"1979","journal-title":"AFIPS Conf Proc 1979 NCC"},{"key":"ref19","first-page":"116","article-title":"circuit switching technology: a state-of-the-art survey","author":"thurber","year":"1978","journal-title":"Proc COMPCON 78"},{"key":"ref28","first-page":"11","article-title":"preliminary design of a versatile parallel image processing system","author":"siegel","year":"1978","journal-title":"Proc 3rd Biennial Conf Computing Indiana"},{"key":"ref4","first-page":"34","article-title":"an implementation of the hadamard transform on the staran associative array processors","author":"krygiel","year":"1976","journal-title":"1976 Int'l Conf Parallel Processing"},{"key":"ref27","first-page":"65","article-title":"the flip network in staran","author":"batcher","year":"1976","journal-title":"1976 Int'l Conf Parallel Processing"},{"key":"ref3","first-page":"327","author":"stone","year":"0","journal-title":"Introduction to Computer Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1972.8647"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/800094.803052"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1977.217824"},{"key":"ref8","first-page":"113","article-title":"efficient high speed computing with the distributed array processor","author":"flanders","year":"1977","journal-title":"Symp on High Speed Computer and Algorithm Organization"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1500175.1500260"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/800255.810659"},{"key":"ref9","first-page":"203","article-title":"a massively parallel processing computer","author":"fung","year":"1977","journal-title":"Symp on High Speed Computer and Algorithm Organization"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674863"},{"key":"ref20","first-page":"89","article-title":"parallel processor architectures part 1: general purpose systems","volume":"18","author":"thurber","year":"1979","journal-title":"Computer Design"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674637"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/356683.356686"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1901","DOI":"10.1109\/PROC.1966.5273","article-title":"very high-speed computing systems","volume":"54","author":"flynn","year":"1966","journal-title":"Proceedings of the IEEE"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.5009294"},{"key":"ref24","author":"thurber","year":"1976","journal-title":"Large Scale Computer Architecture Parallel and Associative Processors"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.1674718"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1978.218313"},{"key":"ref44","first-page":"586","article-title":"partitionable simd computer system interconnection network universality","author":"siegel","year":"1978","journal-title":"17th Annu Allerton Conf Commun Contr Comput"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224157"},{"key":"ref43","first-page":"272","article-title":"single instruction stream-multiple data stream machine interconnection network design","author":"siegel","year":"1976","journal-title":"1976 Int'l Conf Parallel Processing"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/356654.356659"}],"container-title":["Computer"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/2\/34731\/01658780.pdf?arnumber=1658780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:56:43Z","timestamp":1642006603000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1658780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1979,6]]},"references-count":45,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/mc.1979.1658780","relation":{},"ISSN":["0018-9162"],"issn-type":[{"value":"0018-9162","type":"print"}],"subject":[],"published":{"date-parts":[[1979,6]]}}}