{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T02:22:28Z","timestamp":1782958948296,"version":"3.54.5"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-009"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-001"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computer"],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/mc.2023.3318769","type":"journal-article","created":{"date-parts":[[2024,1,3]],"date-time":"2024-01-03T19:30:34Z","timestamp":1704310234000},"page":"75-81","source":"Crossref","is-referenced-by-count":7,"title":["Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications"],"prefix":"10.1109","volume":"57","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1530-7788","authenticated-orcid":false,"given":"Debendra Das","family":"Sharma","sequence":"first","affiliation":[{"name":"CXL Board Technical Task Force, Intel, Santa Clara, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6216-935X","authenticated-orcid":false,"given":"Thomas","family":"Coughlin","sequence":"additional","affiliation":[{"name":"Coughlin Associates, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"issue":"8","key":"ref1","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"Moore","year":"1965","journal-title":"Electronics"},{"key":"ref2","volume-title":"Universal Chiplet Interconnect Express (UCIe): Building an open chiplet ecosystem","author":"Sharma","year":"2022"},{"key":"ref3","volume-title":"Universal Chiplet Interconnect Express (UCIe) specification, Rev 1.0","year":"2022"},{"key":"ref4","volume-title":"PCI Express base specification revision 6.0","year":"2022"},{"key":"ref5","volume-title":"Compute express link 3.0 specification","year":"2022"},{"key":"ref6","volume-title":"Heterogeneous integration roadmap","year":"2021"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2019.2942708"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3235770"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247726"},{"key":"ref11","volume-title":"Universal Chiplet Interconnect Express (UCIe) specification, Rev 1.1","year":"2023"}],"container-title":["Computer"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/2\/10380233\/10380290.pdf?arnumber=10380290","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T05:19:23Z","timestamp":1706073563000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10380290\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":11,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/mc.2023.3318769","relation":{},"ISSN":["0018-9162","1558-0814"],"issn-type":[{"value":"0018-9162","type":"print"},{"value":"1558-0814","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}