{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T17:42:20Z","timestamp":1694626940808},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[1987,7,1]],"date-time":"1987-07-01T00:00:00Z","timestamp":552096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Commun. Mag."],"published-print":{"date-parts":[[1987,7]]},"DOI":"10.1109\/mcom.1987.1093656","type":"journal-article","created":{"date-parts":[[2004,4,29]],"date-time":"2004-04-29T00:28:59Z","timestamp":1083198539000},"page":"62-72","source":"Crossref","is-referenced-by-count":8,"title":["FIR digital filters for high sample rate applications"],"prefix":"10.1109","volume":"25","author":[{"given":"S.","family":"Tewksbury","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Hatamian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Franzon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Hornak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Siller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Lawrence","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"crossref","first-page":"1557","DOI":"10.1109\/T-ED.1987.23119","article-title":"on the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures","volume":"34","author":"hornak","year":"1987","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref38","article-title":"Through-wafer optical interconnects for multi-wafer wafer-scale integrated architectures","author":"hornak","year":"1986","journal-title":"SPIE 30th Symp on Optical and Optoelectronic Applied Sciences and Eng"},{"key":"ref33","article-title":"High density interconnections for advanced packaging","author":"adams","year":"1987","journal-title":"ECS Spring 87"},{"key":"ref32","doi-asserted-by":"crossref","DOI":"10.1109\/ISSCC.1987.1157100","article-title":"Multichip packaging technique for VLSI based systems","author":"levinstein","year":"1987","journal-title":"IEEE 1987 Int Solid-State Cir Conf"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCHMT.1984.1136347"},{"key":"ref30","year":"0"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1984.12943"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1117\/12.939377","article-title":"Optical interconnects in microelectronics","volume":"456","author":"goodman","year":"1984","journal-title":"Proc SPIE"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1986.1156981"},{"key":"ref34","author":"johnson","year":"1986","journal-title":"Wafer-Scale Integration"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"479","DOI":"10.1109\/T-ED.1985.21966","article-title":"a wafer-scale digital integrator using restructurable vsli","volume":"32","author":"raffel","year":"1985","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref27","first-page":"34","article-title":"Computer-aided design and fabrication of wafer-scale integration","author":"dolan","year":"1985","journal-title":"VLSI Design"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCHMT.1987.1134701"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083369"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TAU.1968.1162002"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223261"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1983.1164165"},{"key":"ref21","first-page":"273","author":"ramachandran","year":"1986","journal-title":"VLSI Signal Processing II"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCHMT.1983.1136188"},{"key":"ref23","year":"0"},{"key":"ref26","year":"1986","journal-title":"Wafer Scale Integration"},{"key":"ref25","year":"1986","journal-title":"Wafer Scale Integration"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052566"},{"key":"ref51","article-title":"Fundamental interconnection limits","author":"franzon","year":"0","journal-title":"AT&T Tech Jour"},{"key":"ref52","first-page":"13","author":"genestier","year":"1986","journal-title":"Wafer-Scale Integration"},{"key":"ref10","author":"rao","year":"1985","journal-title":"Regular Iterative Algorithms and their implementation on Processor arrays"},{"key":"ref11","first-page":"30","article-title":"Implications and projections of gallium arsenide technology in high speed computing","author":"eden","year":"1983","journal-title":"Proc 1983 Int Conf Comp Design VLSI in Computers"},{"key":"ref40","first-page":"127","author":"fried","year":"1986","journal-title":"Wafer-Scale Integration"},{"key":"ref12","first-page":"451","author":"gilbert","year":"1985","journal-title":"VLSI and Modern Signal Processing"},{"key":"ref13","first-page":"103","author":"noll","year":"1987","journal-title":"Systolic Arrays"},{"key":"ref14","first-page":"316","author":"yassaie","year":"1986","journal-title":"VLSI Signal Processing II"},{"key":"ref15","first-page":"277","author":"ahmed","year":"1985","journal-title":"VLSI and Modern Signal Processing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1976.1050797"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093315"},{"key":"ref18","first-page":"16.9.1","article-title":"Adder-based digital signal processor architectures for 80 nsec cycle time","author":"ranier","year":"1984","journal-title":"Proc 1984 Int Conf Acoust Speech Sig Proc"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1049\/ip-g-1.1982.0008"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1981.tb00278.x"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1982.1163937"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1986.1169046"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1985.13218"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675922"},{"key":"ref49","first-page":"118","article-title":"A symmetric clock-distribution tree and optimized highspeed interconnections for reduced clock skew in ULSI and WSI circuits","author":"bakoglu","year":"1986","journal-title":"IEEE Int Conf Comp Design VLSI in Computers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052427"},{"key":"ref9","first-page":"370","article-title":"On the implementation and use of systolic array processors","author":"kung","year":"1983","journal-title":"Proc 1983 Int Conf Comp Design VLSI in Computers"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052564"},{"key":"ref45a","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1986.1168842"},{"key":"ref45b","doi-asserted-by":"crossref","first-page":"1192","DOI":"10.1109\/PROC.1987.13872","article-title":"parallel bit-level pipelined vlsi designs for high-speed signal processing","volume":"75","author":"hatamian","year":"1987","journal-title":"Proceedings of the IEEE"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1117\/12.933696"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1067649.801713"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.1676584"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1016\/0026-2714(84)90477-3"},{"key":"ref44","first-page":"207","author":"franzon","year":"1986","journal-title":"Systolic Arrays"},{"key":"ref43","first-page":"230","article-title":"Interconnect strategies for fault-tolerant 2D VLSI arrays","author":"franzon","year":"1986","journal-title":"Int Conf Computer Design VLSI in Computers"}],"container-title":["IEEE Communications Magazine"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/35\/23880\/01093656.pdf?arnumber=1093656","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:19:11Z","timestamp":1642004351000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1093656\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,7]]},"references-count":53,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/mcom.1987.1093656","relation":{},"ISSN":["0163-6804"],"issn-type":[{"value":"0163-6804","type":"print"}],"subject":[],"published":{"date-parts":[[1987,7]]}}}