{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T05:40:03Z","timestamp":1744436403578,"version":"3.40.4"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Commun. Mag."],"published-print":{"date-parts":[[2003,12]]},"DOI":"10.1109\/mcom.2003.1252802","type":"journal-article","created":{"date-parts":[[2003,12,22]],"date-time":"2003-12-22T15:42:26Z","timestamp":1072107746000},"page":"76-84","source":"Crossref","is-referenced-by-count":46,"title":["Gigabit ethernet switches using a shared buffer architecture"],"prefix":"10.1109","volume":"41","author":[{"given":"M.V.","family":"Lau","sequence":"first","affiliation":[]},{"given":"S.","family":"Shieh","sequence":"additional","affiliation":[]},{"family":"Pei-Feng Wang","sequence":"additional","affiliation":[]},{"given":"B.","family":"Smith","sequence":"additional","affiliation":[]},{"given":"D.","family":"Lee","sequence":"additional","affiliation":[]},{"given":"J.","family":"Chao","sequence":"additional","affiliation":[]},{"given":"B.","family":"Shung","sequence":"additional","affiliation":[]},{"family":"Cheng-Chung Shih","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"volume-title":"Computer Networks","year":"1996","author":"Tanenbaum","key":"ref1"},{"volume-title":"Interconnections","year":"1999","author":"Perlman","key":"ref2"},{"volume-title":"The Switch Book \u2013 The Complete Guide to LAN Switching Technology","year":"2000","author":"Seifert","key":"ref3"},{"volume-title":"MPLS \u2013 Technology and Applications","year":"2000","author":"Davie","key":"ref4"},{"key":"ref5","first-page":"52","article-title":"A Packet-memory-integrated 44 Gb\/s Switching Processor with a 10Gb Port and 12 Gb Ports","author":"Lau","year":"2002","journal-title":"ISSCC Dig. Tech. Papers"},{"key":"ref6","article-title":"A 2.5 Tb\/s LCS Switch Core","volume-title":"Conf. Record, HotChip-13","author":"NcKeown","year":"2001"},{"article-title":"Media Access Control (MAC) Bridges","volume-title":"ANSI\/IEEE Std 802.1D","year":"1998","key":"ref7"},{"author":"Lee","key":"ref8","article-title":"Method and Apparatus for High Speed Table Search"},{"key":"ref9","article-title":"An Efficient Architecture for Multicasting in Shared Buffer ATM Switches","author":"Lin","year":"1998","journal-title":"IEICE Trans. Commun., special issue on ATM Systems in Broadband Networks"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2000.880671"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.799867"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.726562"}],"container-title":["IEEE Communications Magazine"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/35\/28028\/01252802.pdf?arnumber=1252802","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T05:02:13Z","timestamp":1744434133000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1252802\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,12]]},"references-count":12,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2003,12]]}},"URL":"https:\/\/doi.org\/10.1109\/mcom.2003.1252802","relation":{},"ISSN":["0163-6804"],"issn-type":[{"type":"print","value":"0163-6804"}],"subject":[],"published":{"date-parts":[[2003,12]]}}}