{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:35:06Z","timestamp":1765355706990},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/mdat.2013.2255912","type":"journal-article","created":{"date-parts":[[2013,3,29]],"date-time":"2013-03-29T18:01:34Z","timestamp":1364580094000},"page":"54-62","source":"Crossref","is-referenced-by-count":5,"title":["Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems"],"prefix":"10.1109","volume":"30","author":[{"given":"Zhenglin","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingchun","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongfang","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuecheng","family":"Zou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","author":"suh","year":"2005","journal-title":"AEGIS A Single-Chip Secure Processor"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1165389.945463"},{"key":"ref10","article-title":"The Galois\/Counter Mode of Operation (GCM)","author":"mcgrew","year":"2005","journal-title":"Nat Inst Standards Technol Updated Submission to Modes of Operation Process"},{"key":"ref6","first-page":"289","article-title":"TEC-tree: A low cost and parallelizable tree for efficient defense against memory replay attacks","author":"elbaz","year":"2007","journal-title":"Proc Cryptographic Hardware and Embedded Systems (CHES)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/WICOM.2010.5600189"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-17499-5_10"},{"key":"ref8","article-title":"Configurable memory security in embedded systems","volume":"v","author":"crenne","year":"2011","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-17569-5_36"},{"key":"ref2","first-page":"1","article-title":"Hardware mechanisms for memory authentication: A survey of existing techniques and engines","volume":"5430","author":"elbaz","year":"2009","journal-title":"Transactions on Computational Science I"},{"key":"ref9","year":"2007","journal-title":"Recommendation for Block Cipher Mode of Operation Galois\/counter Mode (GCM) and (GMAC)"},{"key":"ref1","author":"vaslin","year":"2008","journal-title":"Hardware Core for Off-Chip Memory Security Management in Embedded Systems"}],"container-title":["IEEE Design &amp; Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/6687242\/06490339.pdf?arnumber=6490339","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:43:42Z","timestamp":1642005822000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6490339\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":11,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2013.2255912","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"value":"2168-2356","type":"print"},{"value":"2168-2364","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10]]}}}