{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:36Z","timestamp":1759147116444},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,8,1]],"date-time":"2014-08-01T00:00:00Z","timestamp":1406851200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/mdat.2014.2304437","type":"journal-article","created":{"date-parts":[[2014,2,4]],"date-time":"2014-02-04T19:03:37Z","timestamp":1391540617000},"page":"16-26","source":"Crossref","is-referenced-by-count":10,"title":["On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs"],"prefix":"10.1109","volume":"31","author":[{"family":"Chun-Chuan Chi","sequence":"first","affiliation":[]},{"family":"Bing-Yang Lin","sequence":"additional","affiliation":[]},{"family":"Cheng-Wen Wu","sequence":"additional","affiliation":[]},{"family":"Min-Jer Wang","sequence":"additional","affiliation":[]},{"family":"Hung-Chih Lin","sequence":"additional","affiliation":[]},{"family":"Ching-Neng Peng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248968"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796763"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139181"},{"key":"ref10","first-page":"118","article-title":"3D-IC interconnect test, diagnosis, repair","author":"chi","year":"0","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref5","first-page":"1277","article-title":"Challenges and emerging solutions in testing TSV-based 2.5D- and 3D-Stacked ICs","author":"marinissen","year":"2012","journal-title":"Proc Design Autom Test Eur"},{"key":"ref11","first-page":"52","article-title":"Interconnect testing with boundary scan","author":"wagner","year":"0","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"key":"ref12","year":"2011"},{"key":"ref7","year":"2001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2198475"}],"container-title":["IEEE Design & Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/6873371\/06731552.pdf?arnumber=6731552","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:31:18Z","timestamp":1642005078000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6731552\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":12,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2014.2304437","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"value":"2168-2356","type":"print"},{"value":"2168-2364","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,8]]}}}