{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:35:10Z","timestamp":1776443710971,"version":"3.51.2"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/mdat.2015.2497322","type":"journal-article","created":{"date-parts":[[2015,11,3]],"date-time":"2015-11-03T19:37:24Z","timestamp":1446579444000},"page":"77-84","source":"Crossref","is-referenced-by-count":2,"title":["FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for &lt;sc&gt;nand&lt;\/sc&gt; Flash Memories"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8535-4905","authenticated-orcid":false,"given":"Syed Azhar Ali","family":"Zaidi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abuduwaili","family":"Tuoheti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maurizio","family":"Martina","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guido","family":"Masera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"190","article-title":"FPGA accelerator of quasi cyclic EG-LDPC codes decoder for NAND flash memories","author":"zaidi","year":"0","journal-title":"Proc Conf Design Arch for Signal Image Process"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265314"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2022318"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2014.2339329"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891098"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"2711","DOI":"10.1109\/18.959255","article-title":"Low-density parity-check codes based on finite geometries: A rediscovery and new results","volume":"47","author":"yu","year":"2001","journal-title":"IEEE Trans Inf Theory"},{"key":"ref12","first-page":"165","article-title":"Rapid prototyping of floating point AWGN channel using high-level synthesis","author":"zaidi","year":"0","journal-title":"Proc Forum Spec Design Lang"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2010.5624816"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2006.888607"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071990"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463664"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558857"}],"container-title":["IEEE Design &amp; Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/7604039\/07317506.pdf?arnumber=7317506","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T02:34:58Z","timestamp":1633919698000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7317506\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":12,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2015.2497322","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"value":"2168-2356","type":"print"},{"value":"2168-2364","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,12]]}}}