{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:23:34Z","timestamp":1764174214867},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,2,1]],"date-time":"2017-02-01T00:00:00Z","timestamp":1485907200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Lamar University Research Enhancement Grant","award":["420224"],"award-info":[{"award-number":["420224"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/mdat.2015.2499272","type":"journal-article","created":{"date-parts":[[2015,11,10]],"date-time":"2015-11-10T19:45:02Z","timestamp":1447184702000},"page":"47-56","source":"Crossref","is-referenced-by-count":22,"title":["Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias"],"prefix":"10.1109","volume":"34","author":[{"given":"Selahattin","family":"Sayil","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Archit H.","family":"Shah","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Md. Adnan","family":"Zaman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad A.","family":"Islam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.853696"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"},{"key":"ref10","article-title":"Analog Integrated Circuit Design","author":"carusone","year":"2011"},{"key":"ref6","first-page":"67","article-title":"Use of pass-transistor logic to minimize the impact of soft errors in combinational circuits","author":"kumar","year":"2005","journal-title":"Proc of Workshop on SELSE"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2015.04.008"},{"key":"ref5","first-page":"133","article-title":"Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits","author":"h","year":"2009","journal-title":"Proc RADECS"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542322"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2012.2218257"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.39"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.25"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2255624"}],"container-title":["IEEE Design &amp; Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/7815449\/07323810.pdf?arnumber=7323810","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:45:23Z","timestamp":1642005923000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7323810\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2015.2499272","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"value":"2168-2356","type":"print"},{"value":"2168-2364","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,2]]}}}