{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T07:34:32Z","timestamp":1743320072595,"version":"3.37.3"},"reference-count":165,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,1]],"date-time":"2021-02-01T00:00:00Z","timestamp":1612137600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Multidisciplinary University Research Initiatives","award":["N00014-16-R-FO05"],"award-info":[{"award-number":["N00014-16-R-FO05"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2021,2]]},"DOI":"10.1109\/mdat.2020.3016587","type":"journal-article","created":{"date-parts":[[2020,8,14]],"date-time":"2020-08-14T20:14:48Z","timestamp":1597436088000},"page":"39-68","source":"Crossref","is-referenced-by-count":11,"title":["Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads"],"prefix":"10.1109","volume":"38","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0227-0421","authenticated-orcid":false,"given":"Brian","family":"Crafton","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Spetalnick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5416-3302","authenticated-orcid":false,"given":"Yan","family":"Fang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8391-0576","authenticated-orcid":false,"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662393"},{"key":"ref38","first-page":"31","article-title":"10×10nm2Hf\/HfO pp. 31–36, IEEE, 2011. crossbar resistive RAM with excellent performance, reliability and low-energy operation","author":"govoreanu","year":"2011","journal-title":"IEDM Tech Dig"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310393"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref31","article-title":"Fixing the train-test resolution discrepancy","author":"touvron","year":"2019","journal-title":"arXiv 1906 06423"},{"journal-title":"Outrageously large neural networks The sparsely-gated mixture-of-experts layer","year":"2017","author":"shazeer","key":"ref30"},{"key":"ref37","first-page":"27","article-title":"High endurance phase change memory chip implemented based on carbon-doped Ge2Sb2Te5 in 40 nm node for embedded application","author":"song","year":"2018","journal-title":"IEDM Tech Dig"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614513"},{"key":"ref35","first-page":"1","article-title":"7.5 a 3.3 ns-access-time 71.2 ?W\/MHz 1 Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","first-page":"258","article-title":"A 64 Mb MRAM with clamped-reference and adequate-reference schemes","author":"tsuchida","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref27","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-019-1724-z"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"ref22","first-page":"18","article-title":"Demonstration of highly manufacturable STT-MRAM embedded in 28 nm logic","author":"song","year":"2018","journal-title":"IEDM Tech Dig"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409716"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838429"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref26","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","author":"krizhevsky","year":"2012","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351338"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-04484-2"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.7567\/JJAPS.26S4.61"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2009"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2014.6889893"},{"key":"ref153","doi-asserted-by":"crossref","first-page":"533","DOI":"10.1038\/323533a0","article-title":"Learning representations by back-propagating errors","volume":"323","author":"rumelhart","year":"1986","journal-title":"Nature"},{"key":"ref156","article-title":"DNNNeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training","author":"peng","year":"2020","journal-title":"arXiv 2003 06471"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2014.2383395"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref152","article-title":"Understanding reuse, performance, and hardware cost of DNN dataflows: A data-centric approach using MAESTRO","author":"kwon","year":"2018","journal-title":"arXiv 1805 02566"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3195998"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382135"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193835"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.55"},{"key":"ref149","first-page":"1","article-title":"Breaking barriers: Maximizing array utilization for compute in-memory fabrics","author":"crafton","year":"2020","journal-title":"Proc IFIP Int Conf Very Large Scale Integr (VLSI-SoC)"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3275"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419330"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2935890"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2016.00056"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6463\/ab37b6"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269271"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1146\/annurev-matsci-082908-145405"},{"key":"ref40","first-page":"226","article-title":"14.3 a 43pJ\/cycle non-volatile microcontroller with 4.7?s shutdown\/wake-up integrating 2.3-bit\/Cell resistive RAM and resilience techniques","author":"wu","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref165","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715066"},{"key":"ref164","article-title":"Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwisefeedforward training","author":"frenkel","year":"2019","journal-title":"arXiv 1909 01311"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2019.00525"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2942367"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778006"},{"key":"ref160","first-page":"1037","article-title":"Direct feedback alignment provides learning in deep neural networks","author":"n\u00f8kland","year":"2016","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref4","first-page":"10","article-title":"1.1 computing’s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541967"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms13276"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173176"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.21.1450"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2017.00538"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2019.8824820"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877289"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796677"},{"key":"ref45","first-page":"200","article-title":"A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160ns MLC-access capability","author":"sheu","year":"2011","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479018"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1063\/1.3564883"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898050"},{"key":"ref41","first-page":"11","article-title":"A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs","author":"trentzsch","year":"2016","journal-title":"IEDM Tech Dig"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164732"},{"key":"ref127","article-title":"Batch normalization: Accelerating deep network training by reducing internal covariate shift","author":"ioffe","year":"2015","journal-title":"arXiv 1502 03167"},{"key":"ref126","first-page":"807","article-title":"Rectified linear units improve restricted Boltzmann machines","author":"nair","year":"2010","journal-title":"Proc 27th Int Conf Mach Learn (ICML)"},{"key":"ref125","first-page":"2017","article-title":"Spatial transformer networks","author":"jaderberg","year":"2015","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.8.1735"},{"key":"ref73","first-page":"1","article-title":"Multilevel phase change memory modeling and experimental characterization","author":"pantazi","year":"2009","journal-title":"Proc EPCOS"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418973"},{"key":"ref129","article-title":"Quantizing deep convolutional networks for efficient inference: A whitepaper","author":"krishnamoorthi","year":"2018","journal-title":"arXiv 1806 08342"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1063\/1.2215621"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201700627"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1063\/1.3653279"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2819190"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112747"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937569"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2012.2214472"},{"key":"ref133","first-page":"2849","article-title":"Fixed point quantization of deep convolutional networks","author":"lin","year":"2016","journal-title":"Proc Int Conf Mach Learn"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1145\/355841.355847"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2018.2865352"},{"key":"ref132","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or -1","author":"courbariaux","year":"2016","journal-title":"arXiv 1602 02830 [cs]"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0054-8"},{"key":"ref136","first-page":"7675","article-title":"Training deep neural networks with 8-bit floating point numbers","author":"wang","year":"2018","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref138","first-page":"5145","article-title":"Scalable methods for 8-bit training of neural networks","author":"banner","year":"2018","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref137","article-title":"Training and inference with integers in deep neural networks","author":"wu","year":"2018","journal-title":"arXiv 1802 04680"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms5314"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2004.831219"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1063\/1.328036"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.888752"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796655"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789723"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1063\/1.4938532"},{"key":"ref141","first-page":"1009","article-title":"MNSIM: Simulation platform for memristor-based neuromorphic computing system","volume":"37","author":"xia","year":"2018","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1063\/1.2773688"},{"key":"ref142","article-title":"RxNN: A framework for evaluating deep neural networks on resistive crossbars","author":"jain","year":"2018","journal-title":"arXiv 1809 00072"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.825805"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749724"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1063\/1.3599559"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1145\/3358176"},{"key":"ref2","first-page":"8024","article-title":"PyTorch: An imperative style, high-performance deep learning library","author":"paszke","year":"2019","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2016.7574617"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"key":"ref1","first-page":"265","article-title":"TensorFlow: A system for large-scale machine learning","author":"abadi","year":"2016","journal-title":"Proc of USENIX Symp on Operating Systems Design and Implementation (OSDI)"},{"journal-title":"Word-line level shift circuit","year":"2012","author":"arsovski","key":"ref109"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6463\/aad6f8"},{"journal-title":"Word line driver circuit for dynamic random access memories","year":"1993","author":"bronner","key":"ref108"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342199"},{"journal-title":"High voltage word line driver","year":"2012","author":"reohr","key":"ref107"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351375"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2014.7008879"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2874880"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946034"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2018.2797887"},{"key":"ref104","first-page":"202","article-title":"A 512 Mb phase-change memory (PCM) in 90 nm CMOS achieving 2b\/cell","author":"close","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2934603"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref111","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179 ?m2 Cell in 40 nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"journal-title":"High voltage wordline driver with a three stage level shifter","year":"2007","author":"wang","key":"ref112"},{"journal-title":"Level shifter for boosting wordline voltage and memory cell performance","year":"2010","author":"cottier","key":"ref110"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2019.00855"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2776198"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2019.2928769"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2914882"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662447"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref12","first-page":"222","article-title":"14.1 a 65 nm 1.1-to-9.1TOPS\/W hybrid-digital-mixed-signal computing platform for accelerating model-based and model-free swarm robotics","author":"cao","year":"2019","journal-title":"IEEE Int Solid- State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2869150"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref15","first-page":"242","article-title":"14.3 a 28 nm SoC with a 1.2 GHz 568 nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref118","first-page":"234","article-title":"14.3 a 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8TOPS\/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter\/intra-macro data reuse","author":"yue","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662302"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614620"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297384"},{"key":"ref17","article-title":"Hardware-aware pruning of DNNs using LFSR-generated pseudo-random indices","author":"karimzadeh","year":"2019","journal-title":"arXiv 1911 04468"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-017-01481-9"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00015"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342213"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196116"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1126\/science.1254642"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547779"},{"key":"ref114","first-page":"4107","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref113","first-page":"211","article-title":"Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization","author":"stojanovic","year":"2002","journal-title":"Proc 28th Eur Solid-State Circuits Conf"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342235"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1021\/nl201040y"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322271"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967037"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-04485-1"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838348"},{"key":"ref123","article-title":"Counting cards: Exploiting weight and variance distributions for robust compute in-memory","author":"crafton","year":"2020","journal-title":"arXiv 2006 03117"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1063\/1.357194"},{"key":"ref86","first-page":"22","article-title":"Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98 nm, SSfor=42 mV\/dec, SSrev=28 mV\/dec, switch-off 0.2 V, and hysteresis-free strategies","author":"lee","year":"2015","journal-title":"IEDM Tech Dig"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1021\/nl071804g"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.116"}],"container-title":["IEEE Design & Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/9374574\/09167253.pdf?arnumber=9167253","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:53:46Z","timestamp":1652194426000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9167253\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2]]},"references-count":165,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2020.3016587","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"type":"print","value":"2168-2356"},{"type":"electronic","value":"2168-2364"}],"subject":[],"published":{"date-parts":[[2021,2]]}}}