{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:58:12Z","timestamp":1780444692545,"version":"3.54.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006503","name":"Space and Naval Warfare Systems Command","doi-asserted-by":"publisher","award":["N660011824048"],"award-info":[{"award-number":["N660011824048"]}],"id":[{"id":"10.13039\/100006503","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test"],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/mdat.2020.3042177","type":"journal-article","created":{"date-parts":[[2020,12,3]],"date-time":"2020-12-03T20:42:33Z","timestamp":1607028153000},"page":"8-18","source":"Crossref","is-referenced-by-count":57,"title":["ALIGN: A System for Automating Analog Layout"],"prefix":"10.1109","volume":"38","author":[{"given":"Tonmoy","family":"Dhar","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kishor","family":"Kunal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yaguang","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Meghna","family":"Madhusudan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jitesh","family":"Poojary","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arvind K.","family":"Sharma","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenbin","family":"Xu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Steven M.","family":"Burns","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ramesh","family":"Harjani","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Desmond A.","family":"Kirkpatrick","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Parijat","family":"Mukherjee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Soner","family":"Yaldiz","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"A general approach for identifying hierarchical symmetry constraints for analog circuit layout","author":"kunal","year":"2020","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.00015"},{"key":"ref12","first-page":"1","article-title":"A customized graph neural network model for guiding analog IC placement","author":"li","year":"2020","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379630"},{"key":"ref14","author":"soto","year":"2017","journal-title":"Discover the Power of OPAL a New High-Level Design Rule Modeling Language"},{"key":"ref15","first-page":"3","article-title":"High performance 14 nm SOI FinFET CMOS technology with 0.0174&#x00B5;m2 embedded DRAM and 15 levels of Cu metallization","author":"lin","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref16","first-page":"64","article-title":"65 nm CMOS technology for low power applications","author":"steegen","year":"2005","journal-title":"IEDM Tech Dig"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.511572"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996609"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/RME.2006.1689934"},{"key":"ref4","author":"graeb","year":"2010","journal-title":"Analog Layout Synthesis A Survey of Topological Approaches"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.75012"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488739"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097172"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357110"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2064490"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.44506"},{"key":"ref1","first-page":"1","article-title":"ALIGN&#x2013; open-source analog layout automation from the ground up","author":"kunal","year":"2019","journal-title":"Proc ACM\/IEEE Design Autom Conf"},{"key":"ref9","first-page":"55","article-title":"GANA: Graph convolutional network based automated netlist annotation for analog circuits","author":"kunal","year":"2020","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878475"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942060"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009137"},{"key":"ref24","year":"2020","journal-title":"ALIGN Analog Layout Intelligently Generated From Netlists"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3326334"}],"container-title":["IEEE Design &amp; Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6221038\/9398951\/09279310.pdf?arnumber=9279310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:53:43Z","timestamp":1652194423000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9279310\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":24,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/mdat.2020.3042177","relation":{},"ISSN":["2168-2356","2168-2364"],"issn-type":[{"value":"2168-2356","type":"print"},{"value":"2168-2364","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}