{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T10:57:44Z","timestamp":1777546664797,"version":"3.51.4"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[1984,8,1]],"date-time":"1984-08-01T00:00:00Z","timestamp":460166400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[1984,8]]},"DOI":"10.1109\/mdt.1984.5005647","type":"journal-article","created":{"date-parts":[[2009,6,2]],"date-time":"2009-06-02T17:05:45Z","timestamp":1243962345000},"page":"21-39","source":"Crossref","is-referenced-by-count":131,"title":["A Survey of Hardware Accelerators Used in Computer-Aided Design"],"prefix":"10.1109","volume":"1","author":[{"given":"Tom","family":"Blank","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1981.1585453"},{"key":"ref38","author":"blank","year":"1982","journal-title":"A Bit Map Architecture and Algorithms for Design Automation"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585505"},{"key":"ref32","first-page":"116","article-title":"software and algorithms for the distributed-array processors","volume":"1","author":"gostic","year":"1979","journal-title":"ICL Technical J"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585521"},{"key":"ref30","first-page":"411","article-title":"employing a distributed array processor in a dedicated gate array layout system","author":"adshead","year":"1982","journal-title":"IEEE Int'l Conf Circuits and Computers"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1976.5009200"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585504"},{"key":"ref35","first-page":"257","author":"hong","year":"1981","journal-title":"A Physical Design Machine"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/PROC.1983.12527","article-title":"wire-routing machinesnew tools for vlsi design","volume":"71","author":"hong","year":"1983","journal-title":"Proc IEEE"},{"key":"ref28","first-page":"285","author":"moore","year":"1959","journal-title":"Shortest Path through a Maze"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1961.5219222"},{"key":"ref29","author":"flanders","year":"1977","journal-title":"High Speed Computer and Algorithm Organization"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222783"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1984.5005573"},{"key":"ref20","first-page":"592","article-title":"using the ibm los gatos logic simulating machine","author":"howard","year":"1983","journal-title":"Proc IEEE Int'l Conf Computer Design VLSI in Computers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585480"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585479"},{"key":"ref24","first-page":"393","article-title":"a hardware router","volume":"4","author":"breuer","year":"1980","journal-title":"J Digital Systems"},{"key":"ref23","first-page":"60","article-title":"software support for the yorktown simulation engine","author":"kronstadt","year":"1982","journal-title":"Proc 19th ACM\/IEEE Design Automation Conf"},{"key":"ref26","first-page":"165","article-title":"a smart memory array processor for two layer path finding","author":"carroll","year":"1981","journal-title":"Proc Second Caltech Conf Very Large Scale Integration"},{"key":"ref25","first-page":"908","article-title":"design of an iterative array maze router","author":"iosupovicz","year":"1980","journal-title":"Proc IEEE Int'l Conf Circuits and Computers"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1983.1585644"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294819"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1109\/DAC.1983.1585641","article-title":"hal; a block level hardware logic simulator","author":"sasaki","year":"1983","journal-title":"Proc ACM\/IEEE Design Automation Conf"},{"key":"ref40","author":"mead","year":"1980","journal-title":"Introduction to VLSI Systems"},{"key":"ref12","author":"brunt","year":"0"},{"key":"ref13","article-title":"cae stations' simulators tackle 1 million gates","year":"1983","journal-title":"Electronic Design"},{"key":"ref14","author":"passmann","year":"0"},{"key":"ref15","author":"harding","year":"1984"},{"key":"ref16","author":"burrier","year":"1982","journal-title":"The Logic Simulation Machine"},{"key":"ref17","first-page":"580","article-title":"introduction to the ibm los gatos logic simulation machine","author":"howard","year":"1983","journal-title":"Proc IEEE Int'l Conf Computer Design VLSI in Computers"},{"key":"ref18","first-page":"584","article-title":"the ibm los gatos logic simulation machine hardware","author":"burggraff","year":"1983","journal-title":"Proc IEEE Int'l Conf Computer Designs VLSI in Computers"},{"key":"ref19","first-page":"588","article-title":"the ibm los gatos logic simulation machine software","author":"kohn","year":"1983","journal-title":"Proc IEEE Int'l Conf Computer Design VLSI in Computers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270024"},{"key":"ref3","author":"barto","year":"1980","journal-title":"A Computer Architecture for Logic Simulation"},{"key":"ref6","author":"futami","year":"0"},{"key":"ref5","author":"dally","year":"1984","journal-title":"The MOSSIM Simulation Engine Architecture and Design"},{"key":"ref8","first-page":"573","article-title":"use of the boeing computer simulator for logic design confirmation and failure diagnostic programs","author":"vanausdal","year":"1971","journal-title":"Advances in the Astronautical Sciences"},{"key":"ref7","author":"scheff","year":"1972","journal-title":"Gate-Level Logic Simulation"},{"key":"ref49","author":"baker","year":"1980","journal-title":"Artwork Analysis Tools for VLSI Circuits"},{"key":"ref9","first-page":"45","article-title":"logic simulation speeded with new special hardware","author":"lineback","year":"1982","journal-title":"Electronics"},{"key":"ref46","article-title":"special purpose hardware for design rule checking","author":"seiler","year":"1981","journal-title":"Proc Caltech Conf VLSI"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1984.1270085"},{"key":"ref48","author":"seiler","year":"1984","journal-title":"A Hardware Assisted Methodology for VLSI Design Rule Checking"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585506"},{"key":"ref42","article-title":"cytocomputer: architecture for parallel image processing","author":"lougheed","year":"1980","journal-title":"Workshop on Picture Data Description and Management"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/800053.801935"},{"key":"ref44","first-page":"135","article-title":"wire routing experiments on a raster pipeline subarray machine","author":"rutenbar","year":"1983","journal-title":"IEEE Int'l Conf Computer-Aided Design"},{"key":"ref43","author":"rutenbar","year":"1983","journal-title":"A Class of Cellular Architectures to Support Physical Design Automation"}],"container-title":["IEEE Design & Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/5005631\/05005647.pdf?arnumber=5005647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:44:09Z","timestamp":1641987849000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5005647\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1984,8]]},"references-count":50,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/mdt.1984.5005647","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[1984,8]]}}}