{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T00:19:43Z","timestamp":1783556383605,"version":"3.55.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2003,1]]},"DOI":"10.1109\/mdt.2003.1173054","type":"journal-article","created":{"date-parts":[[2003,3,7]],"date-time":"2003-03-07T18:58:16Z","timestamp":1047063496000},"page":"60-67","source":"Crossref","is-referenced-by-count":31,"title":["An all-digital DFT scheme for testing catastrophic faults in PLLs"],"prefix":"10.1109","volume":"20","author":[{"given":"F.","family":"Azais","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Y.","family":"Bertrand","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Renovell","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Ivanov","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Tabatabaei","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207869"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1990.114017"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.222167"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510896"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510835"},{"key":"ref6","volume-title":"Phase-Locked Loops: Theory, Design and Applications","author":"Best","year":"1993"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639691"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606615"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805777"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557129"},{"key":"ref11","first-page":"383","article-title":"A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators","volume-title":"Proc. Asian Test Symp.","author":"Aza","year":"1998"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675614"}],"container-title":["IEEE Design &amp; Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/26361\/01173054.pdf?arnumber=1173054","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:09:29Z","timestamp":1742098169000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1173054\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,1]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2003.1173054","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[2003,1]]}}}