{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:15:23Z","timestamp":1773656123997,"version":"3.50.1"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2003,5,1]],"date-time":"2003-05-01T00:00:00Z","timestamp":1051747200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2003,5]]},"DOI":"10.1109\/mdt.2003.1198688","type":"journal-article","created":{"date-parts":[[2003,5,14]],"date-time":"2003-05-14T18:46:26Z","timestamp":1052937986000},"page":"68-77","source":"Crossref","is-referenced-by-count":3,"title":["Benefits of a SoC-specific test methodology"],"prefix":"10.1109","volume":"20","author":[{"given":"M.S.","family":"Quasem","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Zhigang Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.K.","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/54.632877"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894273"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894300"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743146"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/12.241600"},{"key":"ref7","article-title":"Benefits of System-Specific Test Methodology for Systems-on-Chip","volume-title":"tech. report CENG-03\u201305","author":"Quasem","year":"2003"},{"key":"ref8","first-page":"3.2-1","article-title":"Test Strategy for TI\u2019s TMS320AV7100 Device","volume-title":"Proc. Int\u2019l Workshop of Testing Embedded Core-Based System-Chips","author":"Saxena","year":"1998"},{"key":"ref9","first-page":"2.3.1","article-title":"Test Information for Cores: Comparative Analysis and Recommendations","volume-title":"Proc. Int\u2019l Workshop of Testing Embedded Core-Based System-Chips","author":"Quasem","year":"2000"},{"key":"ref10","article-title":"Fault Simulation Methodology for System-on-Chip That Protects Core\u2019s Intellectual Property (IP)","volume-title":"tech. report CENG-03-04","author":"Quasem","year":"2003"},{"key":"ref11","article-title":"A Test Generation Approach for System-on-Silicon That Use Intellectual Property Cores","volume-title":"tech. report CENG- 03\u201303","author":"Jiang","year":"2003"}],"container-title":["IEEE Design & Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/26982\/01198688.pdf?arnumber=1198688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:18:44Z","timestamp":1742098724000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1198688\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,5]]},"references-count":11,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2003.1198688","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[2003,5]]}}}