{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T04:08:37Z","timestamp":1742184517008,"version":"3.38.0"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2003,7,1]],"date-time":"2003-07-01T00:00:00Z","timestamp":1057017600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2003,7]]},"DOI":"10.1109\/mdt.2003.1214347","type":"journal-article","created":{"date-parts":[[2003,7,23]],"date-time":"2003-07-23T15:30:38Z","timestamp":1058974238000},"page":"4-14","source":"Crossref","is-referenced-by-count":2,"title":["A practical methodology for verifying pipelined microarchitectures"],"prefix":"10.1109","volume":"20","author":[{"given":"R.","family":"Hosabettu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Gopalakrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Srivas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"volume-title":"Systematic Verification of Pipelined Micro-processors","year":"2000","author":"Hosabettu","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-58179-0_44"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/52.57892"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48683-6_7"},{"volume-title":"Superscalar Microprocessor Design","year":"1990","author":"Johnson","key":"ref5"},{"journal-title":"Computer Architecture: A Quantitative Approach, Morgan Kaufmann","year":"1990","author":"Hennessy","key":"ref6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/32.345827"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545637"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44585-4_40"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0028740"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.111.0025"}],"container-title":["IEEE Design & Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/27302\/01214347.pdf?arnumber=1214347","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T05:14:23Z","timestamp":1742102063000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1214347\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,7]]},"references-count":11,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2003.1214347","relation":{},"ISSN":["0740-7475"],"issn-type":[{"type":"print","value":"0740-7475"}],"subject":[],"published":{"date-parts":[[2003,7]]}}}