{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:45:05Z","timestamp":1781883905798,"version":"3.54.5"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2003,9,1]],"date-time":"2003-09-01T00:00:00Z","timestamp":1062374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2003,9]]},"DOI":"10.1109\/mdt.2003.1232251","type":"journal-article","created":{"date-parts":[[2003,9,30]],"date-time":"2003-09-30T14:33:34Z","timestamp":1064932414000},"page":"8-16","source":"Crossref","is-referenced-by-count":58,"title":["Delay defect characteristics and testing strategies"],"prefix":"10.1109","volume":"20","author":[{"family":"Kee Sup Kim","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Mitra","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"P.G.","family":"Ryan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011108"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011137"},{"key":"ref3","first-page":"407","article-title":"Validation and Test of Network Processors and ASICs","volume-title":"Proc. 20th IEEE VLSI Test Symp.","author":"Chia","year":"2002"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639630"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207761"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966652"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990304"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041774"},{"key":"ref9","volume-title":"XPAND: Deterministic Test Generation with Very Few Scan Pins and Lots of Scan Chains, tech. report","author":"Mitra","year":"2003"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041773"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.1995.535511"}],"container-title":["IEEE Design &amp; Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/27604\/01232251.pdf?arnumber=1232251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:27:12Z","timestamp":1742099232000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1232251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,9]]},"references-count":11,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2003.1232251","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[2003,9]]}}}