{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T15:15:26Z","timestamp":1775229326172,"version":"3.50.1"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2003,11,1]],"date-time":"2003-11-01T00:00:00Z","timestamp":1067644800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Des. Test. Comput."],"published-print":{"date-parts":[[2003,11]]},"DOI":"10.1109\/mdt.2003.1246159","type":"journal-article","created":{"date-parts":[[2003,11,20]],"date-time":"2003-11-20T23:29:22Z","timestamp":1069370962000},"page":"9-17","source":"Crossref","is-referenced-by-count":35,"title":["Three generations of asynchronous microprocessors"],"prefix":"10.1109","volume":"20","author":[{"given":"A.J.","family":"Martin","sequence":"first","affiliation":[]},{"given":"M.","family":"Nystrom","sequence":"additional","affiliation":[]},{"given":"C.G.","family":"Wong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.21236\/ADA447727"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1997.634853"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199162"},{"key":"ref4","first-page":"237","article-title":"Synthesis of Asynchronous VLSI Circuits","volume-title":"Formal Methods for VLSI Design","author":"Martin","year":"1990"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.21236\/ADA444293"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-6217-4_15"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1997.587182"},{"key":"ref8","volume-title":"Alpha Implementations and Architectures","author":"Bhandakar","year":"1996"},{"key":"ref9","article-title":"General Processor Information","author":"Burd","year":"2000"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1998.666497"}],"container-title":["IEEE Design &amp; Test of Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/54\/27925\/01246159.pdf?arnumber=1246159","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:31:11Z","timestamp":1742099471000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1246159\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,11]]},"references-count":10,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/mdt.2003.1246159","relation":{},"ISSN":["0740-7475"],"issn-type":[{"value":"0740-7475","type":"print"}],"subject":[],"published":{"date-parts":[[2003,11]]}}}