{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:43:12Z","timestamp":1725529392119},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1109\/meco.2013.6601352","type":"proceedings-article","created":{"date-parts":[[2013,9,25]],"date-time":"2013-09-25T18:05:33Z","timestamp":1380132333000},"page":"184-187","source":"Crossref","is-referenced-by-count":0,"title":["Digital to analog converters for CMOS ternary digital systems"],"prefix":"10.1109","author":[{"given":"Zlatko","family":"Bundalo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ferid","family":"Softic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Drazen","family":"Pasalic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dusanka","family":"Bundalo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miroslav","family":"Kostadinovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"538","article-title":"Quaternary cmos combinational logic circuits","author":"patel","year":"2009","journal-title":"Proceedings of International Conference on Information and Multimedia Technology"},{"key":"2","article-title":"Multiple-valued logic in vlsi design","author":"dubrova","year":"2002","journal-title":"International Journal on Multiple-Valued Logic"},{"key":"1","first-page":"340","article-title":"Multiple-valued logic in VLSI: Challenges and opportunities","author":"dubrova","year":"1999","journal-title":"Proceedings of Conference NORCHIP'99"},{"key":"7","article-title":"CMOS and BiCMOS logic circuits for conversion from low to high logic level","author":"bundalo","year":"2007","journal-title":"Proceedings of the 5 1 Conference ETRAN Herceg Novi-Igalo"},{"key":"6","article-title":"Logic circuits for interconnection of ternary and binary CMOS digital circuits and systems","author":"bundalo","year":"0","journal-title":"Proceedings of the 55'h Conference ETRAN Banja Vrueica Bosnia and Herzegovina June 20 1 J"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/43.79495"},{"key":"4","article-title":"Quaternary sequential circuits","author":"patel","year":"0","journal-title":"International Journal of Computer Science and Network Security"}],"event":{"name":"2013 2nd Mediterranean Conference on Embedded Computing (MECO 2013)","start":{"date-parts":[[2013,6,15]]},"location":"Budva","end":{"date-parts":[[2013,6,20]]}},"container-title":["2013 2nd Mediterranean Conference on Embedded Computing (MECO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6590065\/6601312\/06601352.pdf?arnumber=6601352","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T17:01:09Z","timestamp":1580922069000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6601352\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/meco.2013.6601352","relation":{},"subject":[],"published":{"date-parts":[[2013,6]]}}}