{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:57:57Z","timestamp":1747810677710},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,6]]},"DOI":"10.1109\/meco.2018.8406004","type":"proceedings-article","created":{"date-parts":[[2018,7,9]],"date-time":"2018-07-09T23:17:35Z","timestamp":1531178255000},"page":"1-5","source":"Crossref","is-referenced-by-count":4,"title":["Clock domain crossing \u2014 An advanced course for future digital design engineers"],"prefix":"10.1109","author":[{"given":"Matej","family":"Bartik","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2086075"},{"journal-title":"WP-01082-1 2_Understanding Metastability in FPGAs","year":"2009","author":"stephenson","key":"ref11"},{"journal-title":"Clock domain crossing guidelines for design and verification success","year":"2008","author":"faris","key":"ref12"},{"key":"ref13","first-page":"108","article-title":"Massive Digital Design Education for Large Amount of Undergraduate Students","author":"be?v\u00e0?","year":"2006","journal-title":"Proceedings of EWME 2006 Stockholm Royal Institute of Technology"},{"key":"ref14","first-page":"115","article-title":"Contemporary Methods of Digital Design Education","author":"kub\u00e1tov\u00e1","year":"2005","journal-title":"Electronic Circuits and Systems Conference Bratislava FEI Slovak University of Technology"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2016.7525723"},{"journal-title":"Digilentinc","article-title":"Basys 2 Reference Manual","year":"0","key":"ref16"},{"journal-title":"Xilinx ISE design suite","year":"0","key":"ref17"},{"journal-title":"Digilent Pmod Interface Specification","year":"0","key":"ref18"},{"journal-title":"FT230X USB TO BASIC UART IC FTDI","year":"0","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2010.11.014"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCPEIC.2015.7259493"},{"key":"ref6","first-page":"1","article-title":"ST 424:2012-SMPTE Standard-3 Gb\/s Signal\/Data Serial Interface","year":"2012","journal-title":"SMPTE ST 424 2012"},{"key":"ref5","first-page":"1","article-title":"ST 2022-6:2012-SMPTE Standard-Transport of High Bit Rate Media Signals over IP Networks (HBRMT)","year":"2012","journal-title":"SMPTE ST 2022-6 2012"},{"journal-title":"FPGA-FAQ 0017-Tell me about Metastability","year":"2013","author":"freidin","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISDEA.2010.288"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2016.0399"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MECO.2016.7525779"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICEMI.2009.5274693"},{"journal-title":"XAPP 462-Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs Xilinx","year":"0","key":"ref20"}],"event":{"name":"2018 7th Mediterranean Conference on Embedded Computing (MECO)","start":{"date-parts":[[2018,6,10]]},"location":"Budva, Montenegro","end":{"date-parts":[[2018,6,14]]}},"container-title":["2018 7th Mediterranean Conference on Embedded Computing (MECO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8399137\/8405943\/08406004.pdf?arnumber=8406004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T14:33:43Z","timestamp":1643207623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8406004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/meco.2018.8406004","relation":{},"subject":[],"published":{"date-parts":[[2018,6]]}}}