{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T17:59:36Z","timestamp":1772042376982,"version":"3.50.1"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T00:00:00Z","timestamp":1686009600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T00:00:00Z","timestamp":1686009600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,6,6]]},"DOI":"10.1109\/meco58584.2023.10155108","type":"proceedings-article","created":{"date-parts":[[2023,6,26]],"date-time":"2023-06-26T18:06:51Z","timestamp":1687802811000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["A New RISC-V CPU for Safety-Critical Systems"],"prefix":"10.1109","author":[{"given":"J\u00e1n","family":"Mach","sequence":"first","affiliation":[{"name":"Institute of Computer Engineering and Applied Informatics, Slovak University of Technology,Bratislava,Slovakia,842 16"}]},{"given":"Luk\u00e1\u0161","family":"Koh\u00fatka","sequence":"additional","affiliation":[{"name":"Institute of Informatics, Information Systems and Software Engineering, Slovak University of Technology,Bratislava,Slovakia,842 16"}]},{"given":"Pavel","family":"\u010ci\u010d\u00e1k","sequence":"additional","affiliation":[{"name":"Institute of Computer Engineering and Applied Informatics, Slovak University of Technology,Bratislava,Slovakia,842 16"}]}],"member":"263","reference":[{"key":"ref13","year":"0","journal-title":"Spike RISC-V ISA Simulator Repository"},{"key":"ref12","year":"0","journal-title":"RISCV-DV Random Instruction Generator Repository"},{"key":"ref14","year":"0","journal-title":"EEMBC CoreMark"},{"key":"ref11","year":"0","journal-title":"ARM IHI 0033A AMBA® 3 AHB-Lite Protocol v1 0"},{"key":"ref10","year":"0","journal-title":"The RISC-V Instruction Set Manual Volume I Unprivileged ISA Document Version 20191213"},{"key":"ref2","year":"2011","journal-title":"Rad-Hard 32 bit SPARC V8 Processor AT697F Rev 7703E-AER O-08\/11"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.35"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IECON43393.2020.9255188"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS48698.2020.9081185"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2010.2041234"},{"key":"ref3","author":"cobham","year":"2020","journal-title":"GR740 Radiation Summary"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2018.2799799"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2013237"}],"event":{"name":"2023 12th Mediterranean Conference on Embedded Computing (MECO)","location":"Budva, Montenegro","start":{"date-parts":[[2023,6,6]]},"end":{"date-parts":[[2023,6,10]]}},"container-title":["2023 12th Mediterranean Conference on Embedded Computing (MECO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10154895\/10154897\/10155108.pdf?arnumber=10155108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,17]],"date-time":"2023-07-17T17:31:25Z","timestamp":1689615085000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10155108\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,6]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/meco58584.2023.10155108","relation":{},"subject":[],"published":{"date-parts":[[2023,6,6]]}}}