{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:38:53Z","timestamp":1729654733328,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/memcod.2006.1695900","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T13:01:13Z","timestamp":1158930073000},"page":"49-58","source":"Crossref","is-referenced-by-count":2,"title":["Low-power hardware synthesis from TRS-based specifications"],"prefix":"10.1109","author":[{"given":"G.","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.K.","family":"Shukla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.777880"},{"year":"0","key":"15"},{"key":"16","doi-asserted-by":"crossref","first-page":"536","DOI":"10.1109\/82.847069","article-title":"Low-Power Scheduling with Resources Operating at Multiple Voltages","volume":"47","author":"shiue","year":"2000","journal-title":"IEEE Transactions on Circuits and Systems - II Analog and Digital Signal Processing"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/43.811321"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968703"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545599"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597186"},{"key":"3","article-title":"Hardware Synthesis from Term Rewriting Systems","author":"hoe","year":"1999","journal-title":"Proceeding of VLSI"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9781139172752","author":"baader","year":"1998","journal-title":"Term Rewriting and All That"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382681"},{"year":"0","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5433-2_2"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1998.646573"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5199-7"},{"journal-title":"Spark A Parallelizing Approach to the High-Level Synthesis of Digital Circuits","year":"0","author":"gupta","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2007.016036"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2007.016036"}],"event":{"name":"Fourth ACM & IEEE International Conference on Formal Methods and Models for Co-Design. (MEMOCODE'06)","acronym":"MEMCOD-06","location":"Napa, CA, USA"},"container-title":["Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11148\/35734\/01695900.pdf?arnumber=1695900","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,21]],"date-time":"2019-04-21T04:49:19Z","timestamp":1555822159000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1695900\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/memcod.2006.1695900","relation":{},"subject":[]}}