{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T02:48:20Z","timestamp":1725504500013},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1109\/memcod.2008.4547693","type":"proceedings-article","created":{"date-parts":[[2008,6,20]],"date-time":"2008-06-20T15:40:32Z","timestamp":1213976432000},"page":"79-88","source":"Crossref","is-referenced-by-count":0,"title":["A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study"],"prefix":"10.1109","author":[{"given":"Steve","family":"Haynal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timothy","family":"Kam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emily","family":"Shriver","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinning","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"13"},{"journal-title":"SystemVerilog 3 1a Language Reference Manual","year":"0","key":"11"},{"journal-title":"Verific","year":"0","key":"12"},{"journal-title":"Refactoring Improving the Design of Existing Code","year":"1999","author":"fowler","key":"3"},{"journal-title":"Larry Doolittle and Vincenzo Liguori Vhd2v1","year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/40.216745"},{"journal-title":"Modeling with System Verilog in a Synopsys Synthesis Design Flow","year":"2006","author":"sutherland","key":"10"},{"year":"0","key":"7"},{"journal-title":"Reuse Methodology Manual for System-on-a-Chip Designs","year":"2002","author":"keating","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.314"},{"year":"0","key":"4"},{"article-title":"the integrated design and validation system, memocode keynote","year":"2006","author":"seger","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSS.2000.874022"}],"event":{"name":"2008 6th ACM\/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE '08)","start":{"date-parts":[[2008,6,5]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2008,6,7]]}},"container-title":["2008 6th ACM\/IEEE International Conference on Formal Methods and Models for Co-Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4542603\/4547672\/04547693.pdf?arnumber=4547693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T23:06:59Z","timestamp":1489705619000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4547693\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/memcod.2008.4547693","relation":{},"subject":[],"published":{"date-parts":[[2008,6]]}}}