{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T20:05:45Z","timestamp":1725653145391},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,7]]},"DOI":"10.1109\/memcod.2011.5970510","type":"proceedings-article","created":{"date-parts":[[2011,8,3]],"date-time":"2011-08-03T22:16:29Z","timestamp":1312409789000},"page":"51-60","source":"Crossref","is-referenced-by-count":3,"title":["Formal modelling and transformations of processor instruction sets"],"prefix":"10.1109","author":[{"given":"Andrey","family":"Mokhov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Danil","family":"Sokolov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maxim","family":"Rykunov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Yakovlev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Synchronization and Arbitration in Digital Systems","year":"2008","author":"kinniment","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46611-8_1"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"de micheli","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2010.30"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2008.4574604"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.58"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1706299.1706313"},{"key":"ref17","article-title":"Automated generation of processor architectures in embedded systems design","author":"rykunov","year":"2010","journal-title":"Technical Report NCL-EECE-MSD-TR-2010–164 Newcastle University"},{"key":"ref18","article-title":"Task scheduling based on energy token model","author":"sokolov","year":"2011","journal-title":"Workshop Micro Power Manage Macro Syst Chip (uPM2SoC)"},{"key":"ref19","article-title":"Principles of Asynchronous Circuit Design","author":"spar?","year":"2001","journal-title":"A System Perspective"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.441.0048"},{"journal-title":"Lattice Theory","year":"1967","author":"birkhoff","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14052-5_18"},{"key":"ref5","article-title":"Logic synthesis of asynchronous controllers and interfaces","author":"cortadella","year":"2002","journal-title":"Advanced Microelectronics"},{"key":"ref8","first-page":"234","article-title":"Formal verification of IA-64 division algorithms","author":"harrison","year":"2000","journal-title":"Theorem Proving in Higher Order Logics (TPHOLs)"},{"article-title":"ARM System-on-Chip Architecture","year":"2000","author":"steve","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2692-6"},{"journal-title":"The Workcraft Framework Homepage","year":"2009","key":"ref1"},{"article-title":"Microprocessor architectures RISC, CISC and DSP","year":"1995","author":"heath","key":"ref9"},{"key":"ref20","article-title":"Towards power elastic systems through concurrency management","author":"xia","year":"2010","journal-title":"Technical Report"},{"key":"ref21","article-title":"A Generic Instruction Set Architecture Model in Event-B for Early Design Space Exploration","author":"yuan","year":"2009","journal-title":"Technical Report CSTR-09-006"}],"event":{"name":"2011 9th IEEE\/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2011)","start":{"date-parts":[[2011,7,11]]},"location":"Cambridge, United Kingdom","end":{"date-parts":[[2011,7,13]]}},"container-title":["Ninth ACM\/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5959846\/5970502\/05970510.pdf?arnumber=5970510","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T04:14:04Z","timestamp":1490069644000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5970510\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,7]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/memcod.2011.5970510","relation":{},"subject":[],"published":{"date-parts":[[2011,7]]}}}