{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T01:00:57Z","timestamp":1725670857993},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/memcod.2015.7340486","type":"proceedings-article","created":{"date-parts":[[2015,12,3]],"date-time":"2015-12-03T16:13:03Z","timestamp":1449159183000},"page":"188-197","source":"Crossref","is-referenced-by-count":3,"title":["Symbolic loop parallelization for balancing I\/O and memory accesses on processor arrays"],"prefix":"10.1109","author":[{"given":"Alexandru","family":"Tanase","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Witterauf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jurgen","family":"Teich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"293","article-title":"Efficient Tiled Loop Generation: D-Tiling","author":"kim","year":"2009","journal-title":"Workshop on Languages and Compilers for Parallel Computing (LCPC) volume 5898 of Lecture Notes in Computer Science (LNCS)"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1362622.1362691"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/IPDPS.2007.370291"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/1250734.1250780"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1145\/2160910.2160912"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/MEMCOD.2014.6961865"},{"key":"ref16","article-title":"Parametric tiling of affine loop nests","author":"tavarageri","year":"2010","journal-title":"15th Workshop on Compilers for Parallel Computers"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1524\/itit.2008.0499"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/s11265-014-0905-0"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ISCAS.1989.100823"},{"year":"2001","author":"eckhardt","journal-title":"Algorithmus-Architektur-Codesign f&#x00FC;r den Entwurf digitaler Systeme mit eingebettetem Prozessorarray und Speicherhierarchie","key":"ref4"},{"key":"ref3","first-page":"815","article-title":"A constructive solution to the juggling problem in systolic array synthesis","author":"darte","year":"2000","journal-title":"Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS00"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/43.739055"},{"key":"ref5","first-page":"131","article-title":"Co-partitioning &#x2013; A method for hard-ware\/software codesign for scalable systolic arrays","author":"eckhardt","year":"1997","journal-title":"Reconfigurable Architectures"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/IPDPS.2010.5470459"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/2584660"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1006\/jpdc.1995.1105"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/ASAP.1992.218583"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/1542275.1542301"},{"key":"ref20","first-page":"329","article-title":"Systematic design of local processor arrays for numerical algorithms","author":"thiele","year":"1991","journal-title":"Proc of the Int Workshop on Algorithms and Parallel VLSI Architectures Volume A Tutorials"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"360","DOI":"10.1109\/SPDP.1995.530706","article-title":"On symbolic scheduling and parallel complexity of loops","author":"yang","year":"1995","journal-title":"Proc IEEE Symp Parallel and Distributed Processing"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1145\/1735970.1736044"},{"key":"ref23","article-title":"Parametrically tiled distributed memory parallelization of polyhedral programs","author":"yuki","year":"2013","journal-title":"Technical Report"}],"event":{"name":"2015 ACM\/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)","start":{"date-parts":[[2015,9,21]]},"location":"Austin, TX","end":{"date-parts":[[2015,9,23]]}},"container-title":["2015 ACM\/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7329076\/7340456\/07340486.pdf?arnumber=7340486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T18:13:00Z","timestamp":1580926380000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7340486\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/memcod.2015.7340486","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}