{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T22:25:07Z","timestamp":1725747907075},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,11]]},"DOI":"10.1109\/memcod.2016.7797750","type":"proceedings-article","created":{"date-parts":[[2016,12,29]],"date-time":"2016-12-29T16:54:22Z","timestamp":1483030462000},"page":"78-84","source":"Crossref","is-referenced-by-count":10,"title":["Clocks vs. instants relations: Verifying CCSL time constraints in UML\/MARTE models"],"prefix":"10.1109","author":[{"given":"Judith","family":"Peters","sequence":"first","affiliation":[]},{"given":"Nils","family":"Przigoda","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Wille","sequence":"additional","affiliation":[]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SIES.2010.5551372"},{"journal-title":"UML Profile for MARTE Modeling and Analysis of Real-Time Embedded Systems","article-title":"Object Management Group","year":"2011","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744775"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2011.5970507"},{"key":"ref11","article-title":"Clock Constraints in UML\/MARTE CCSL","author":"andr\u00e9","year":"2008","journal-title":"Institut National de Recherche en Informatique et en Automatique"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2012.6380695"},{"key":"ref12","first-page":"337","article-title":"Z3: an efficient SMT solver","author":"de moura","year":"2008","journal-title":"Tools and Algorithms for Construction and Analysis of Systems"},{"key":"ref8","article-title":"Correct Transformation from CCSL to Promela for verification","author":"mallet","year":"2012","journal-title":"Institut National de Recherche en Informatique et en Automatique"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCS.2014.24"},{"journal-title":"OMG Systems Modeling Language (OMG SysML&#x2122;) Object Management Group","article-title":"Object Management Group","year":"2012","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCS.2011.14"},{"key":"ref1","first-page":"53","article-title":"Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing","author":"drechsler","year":"2012","journal-title":"Forum on specification and Design Languages (FDL)"}],"event":{"name":"2016 ACM\/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","start":{"date-parts":[[2016,11,18]]},"location":"Kanpur, India","end":{"date-parts":[[2016,11,20]]}},"container-title":["2016 ACM\/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7786794\/7797738\/07797750.pdf?arnumber=7797750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,2]],"date-time":"2017-10-02T22:37:37Z","timestamp":1506983857000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7797750\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,11]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/memcod.2016.7797750","relation":{},"subject":[],"published":{"date-parts":[[2016,11]]}}}