{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T09:57:14Z","timestamp":1730282234977,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/mesa.2018.8449144","type":"proceedings-article","created":{"date-parts":[[2018,8,30]],"date-time":"2018-08-30T18:04:36Z","timestamp":1535652276000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Accelerating Viterbi Algorithm using Custom Instruction Approach"],"prefix":"10.1109","author":[{"given":"Waqar","family":"Ahmad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Imran Hafeez","family":"Abbassi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Usman","family":"Sanwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hasan","family":"Mahmood","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(74)90870-5"},{"key":"ref11","first-page":"1","article-title":"The Viterbi Algorithm: A Personal History","author":"forney","year":"2005","journal-title":"Viterbi Conference on Advancing Technology through Communications Sciences"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1186\/1687-6180-2013-118"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/40.848473"},{"key":"ref14","article-title":"Channel Coding Standards in Mobile Communications","author":"grech","year":"1999","journal-title":"Helsinki University of Technology"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2011","author":"hennessy","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2013.6664782"},{"journal-title":"Nios II Core Implementation Details","year":"0","key":"ref17"},{"year":"0","key":"ref18"},{"key":"ref19","first-page":"33","article-title":"Time and Energy Efficient Viterbi Decoding using FPGAs","volume":"5","author":"ou","year":"2005","journal-title":"Acoustics Speech and Signal Processing"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2014.05.007"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2008.4570793"},{"journal-title":"An Efficient Viterbi Decoder Implementation for the ZSP500 DSP Core","year":"0","author":"wilson","key":"ref27"},{"journal-title":"Channel Coding for Telecommunications","year":"1999","author":"bossert","key":"ref3"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1016\/j.proeng.2012.01.834","article-title":"Design and Implementation of Low Power High Speed Viterbi Decoder","volume":"30","author":"k","year":"2012","journal-title":"Procedia Engineering"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1878921.1878933"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995262"},{"year":"2017","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-2317-1_4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1973.9030"},{"key":"ref1","first-page":"1215","article-title":"The Efficient Implementation of S8 AES Algorithm","author":"ahmed","year":"2011","journal-title":"Proceedings of World Congress on Engineering"},{"key":"ref20","volume":"1","author":"palnitkar","year":"2003","journal-title":"Verilog HDL A Guide to Digital Design and Synthesis"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.1992.276674"},{"year":"0","key":"ref21"},{"key":"ref24","first-page":"1","article-title":"Custom Instruction for NIOS II Processor FFT Implementation for Image Processing","volume":"9871","author":"sundararajana","year":"2016","journal-title":"Sensing and Analysis Technologies for Biomedical and Cognitive Applications 2016"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/514144.514731"},{"journal-title":"Technical Report Convolutional Coding on Xtensa Processors Application Note","year":"0","key":"ref26"},{"journal-title":"Structured Computer Organization","year":"2016","author":"tanenbaum","key":"ref25"}],"event":{"name":"2018 14th IEEE\/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA)","start":{"date-parts":[[2018,7,2]]},"location":"Oulu","end":{"date-parts":[[2018,7,4]]}},"container-title":["2018 14th IEEE\/ASME International Conference on Mechatronic and Embedded Systems and Applications (MESA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8430098\/8449143\/08449144.pdf?arnumber=8449144","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T11:43:24Z","timestamp":1643197404000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8449144\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/mesa.2018.8449144","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}