{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T20:53:27Z","timestamp":1775681607785,"version":"3.50.1"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1109\/micro.2002.1176251","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T11:35:00Z","timestamp":1056627300000},"page":"208-218","source":"Crossref","is-referenced-by-count":29,"title":["Compiler-directed instruction cache leakage optimization"],"prefix":"10.1109","author":[{"given":"W.","family":"Zhang","sequence":"first","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.S.","family":"Hu","sequence":"additional","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Degalahal","sequence":"additional","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Kandemir","sequence":"additional","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.J.","family":"Irwin","sequence":"additional","affiliation":[{"name":"Microsystems Design Lab., Pennsylvania State Univ., University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106981"},{"key":"ref11","first-page":"330","article-title":"MediaBench: a tool for evaluating and synthesizing multimedia and communications systems","author":"lee","year":"1997","journal-title":"Proceedings of International Symposium on Microarchitecture"},{"key":"ref12","author":"muchnick","year":"1997","journal-title":"Advanced Compiler Design Implementation"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/92.920821"},{"key":"ref15","year":"0"},{"key":"ref16","first-page":"401","article-title":"Staveren. Standby-current reduction for deep sub-micron VLSI CMOS circuits: smart series switch","author":"van","year":"2000","journal-title":"Proc ProRISC\/IEEE Workshop"},{"key":"ref17","author":"wolfe","year":"1996","journal-title":"High Performance Compilers for Parallel Computing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687996"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991109"},{"key":"ref4","article-title":"Three superblock scheduling models for superscalar and superpipelined processors","author":"chang","year":"1991","journal-title":"Technical Report CRHC-91&#x2013;29 Center for Reliable and High-Performance Computing"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1996.495462"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1145\/545214.545231","article-title":"Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bit-lines","author":"heo","year":"2002","journal-title":"Proc 29th Int l Symp Computer Architecture"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1109\/ISCA.2002.1003572","article-title":"Drowsy Caches: Simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"Proc 29th Int l Symp Computer Architecture"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.871328"},{"key":"ref2","year":"0","journal-title":"Berkeley Predictive Model"},{"key":"ref1","article-title":"A static power model for architects","author":"butts","year":"2000","journal-title":"Proceedings of International Symposium on Microarchitecture"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1007\/BF01130405","article-title":"Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design","volume":"13","author":"kuroda","year":"1996","journal-title":"Journal of VLSI Signal Processing Systems"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953288"}],"event":{"name":"Proceedings 35th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-35)","location":"Istanbul, Turkey","start":{"date-parts":[[2002,11,18]]},"end":{"date-parts":[[2002,11,22]]}},"container-title":["35th Annual IEEE\/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8385\/26403\/01176251.pdf?arnumber=1176251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T20:03:43Z","timestamp":1775678623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1176251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/micro.2002.1176251","relation":{},"subject":[],"published":{"date-parts":[[2002]]}}}